Robert H. Klenke, Jerry H. Tucker, Jason M. Blevins
This paper describes a design environment and platform developed to support senior capstone design projects in computer engineering that incorporates the concept of hardware/software codesign. A...
Robert H. Klenke, James H. Aylor
This paper describes a proposed modeling and design environment for teaching the concepts of performance modeling of hardware/software systems to senior computer engineering undergraduate students....
Smarter Memory = Better Performance: Improving Effective Bandwidth for Streams (2007)
Sally A. Mckee, Assaji Aluwihare, Robert H. Klenke, Trevor C. Landon, Trevor C. L, Christopher W. Oliver, ...
Processor speeds are increasing so much faster than memory speeds that within a decade processors may spend most of their time waiting for data. The problem is already acute for computations that...
Dynamic access ordering for streamed computations (2000)
Sally A. Mckee, William A. Wulf, James H. Aylor, Robert H. Klenke, Senior Member, Maximo H. Salinas, ...
AbstractÐMemory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia...
Dynamic Access Ordering for Streamed Computations (2000)
Sally A. Mckee, Wm. A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, ...
Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression....
Access order and effective bandwidth for streams on a direct rambus memory (1999)
Sung I. Hong, Sally A. Mckee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, Wm. A. Wulf
Processor speeds are increasing rapidly, and memory speeds are not keeping up. Streaming computations (such as multi-media or scientific applications) are among those whose performance is most...
A Unified Environment for End-to-End System Design (1998)
Aylor, James H., Klenke, Robert H.
The goal of this project was to create a unified end-to-end design environment which supports the integrated performance and dependability analysis of system level models and has the capability to...
An integrated design environment for performance and dependability analysis (1997)
Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry Johnson, Ramesh Rao, Anup Ghosh
This paper presents a integrated design environment that supports the design and analysis of digital systems from initial concept to the final implementation. The environment supports both system...
R.; “An analysis of fault partitioned parallel test generation (1996)
Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ron Waxman
Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern...
Design and evaluation of dynamic access ordering hardware (1996)
Sally A. Mckee, Assaji Aluwihare, Benjamin H. Clark, Robert H. Klenke, Trevor C. L, Christopher W. Oliver, ...
Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression....
Design and evaluation of dynamic access ordering hardware (1996)
Sally A. Mckee, Assaji Aluwihare, Benjamin H. Clark, Robert H. Klenke, Trevor C. L, Christopher W. Oliver, ...
Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression....
A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs (1995)
Trevor C. Landon, Trevor C. L, Robert H. Klenke, Maximo H. Salinas, Robert H, Kenneth L. Wright, ...
This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for...
Experimental Implementation of Dynamic Access Ordering (1994)
Sally A. Mckee, Robert H. Klenke, Andrew J. Schwab, Wm. A. Wulf, Steven A. Moyer, James H. Aylor, ...
As microprocessor speeds increase, memory bandwidth is rapidly becoming the performance bottleneck in the execution of vector-like algorithms. Although caching provides adequate performance for many...
Experimental Implementation of Dynamic Access Ordering (1993)
Sally A. Mckee, Robert H. Klenke, Andrew J. Schwab, Wm. A. Wulf, Steven A. Moyer, James H. Aylor, ...
As microprocessor speeds increase, memory bandwidth is rapidly becoming the performance bottleneck in the execution of vector-like algorithms. Although caching provides adequate performance for many...
A graphic representation of VHDL models /--by Robert H. Klenke. (1989)
Thesis (M.S.E.E.)--University of Virginia, 1989.