Model Abstraction for Formal Veri cation (2009)
Yee-wing Hsieh, Steven P. Levitan
As the complexity of circuit designs grows, designers look toward formal veri cation to achieve better test coverage for validating complex designs. However, this approach is inherently...
Lightweight Error Correction Coding for System-Level Interconnects (2008)
Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, Senior Member
Abstract—“Lightweight Hierarchical Error Control Coding (LHECC) ” is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for...
Lightweight Error Correction Coding for System-Level Interconnects (2008)
Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, Senior Member
Abstract—“Lightweight Hierarchical Error Control Coding (LHECC) ” is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for...
Modeling and Simulation of Fiber Image Guide Multi-Chip Modules for MOEMS Applications (2008)
Steven P. Levitan, Timothy P. Kurzweg, Jose A. Martinez, Mark Kahrs, Jason Bakos, Jason Boles, ...
Densely integrated systems in the future will incorporate device and communication technologies that span the domains of digital and analog electronics, optics, micro-mechanics, and micro-fluidics....
Optoelectronic Multi-Chip Module Demonstrator System (2008)
Jason D. Bakos, Donald Chiarulli, Steven P. Levitan
Abstract: We present our work on a demonstration prototype of an optoelectronic 3-chip OE-
Short Courses in System-on-a-Chip (SoC) Design (2008)
Ivan S. Kourtev, Ray R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, ...
A contract between the Pittsburgh Digital Greenhouse and The University of Pittsburgh called for the development of a set of three (3) continuing education courses. The original objectives,...
Error Detection and Correction in an Optoelectronic Memory System (2008)
Robert Hofmann, Madhulima P, Steven P. Levitan, Donald Chiarulli
This paper describes the implementation of error detection and correction logic in the optoelectronic cache memory prototype at the University of Pittsburgh. In this project, our goal is to integrate...
Leo Selavo, Donald M. Chiarulli, Steven P. Levitan
There are a variety of factors that can limit the set of allowable code words that are useable on an optical memory block. In this paper, we will primarily consider inter-symbol interference (ISI)...
Chip-to-Chip Multi-point Optoelectronic Interconnections (2008)
Donald M. Chiarulli, Steven P. Levitan, John Hansson, Michael Weisser
Abstract: We present a new class of interconnection solutions for centimeter scale, board and backplane level, optoelectronic interconnections that combines the high density of free space optical...
A Fast Optical Propagation Technique for Modeling MicroOptical Systems (2008)
Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, Donald M. Chiarulli
As designers become more aggressive in introducing optical components to micro-systems, rigorous optical models are required for system-level simulation tools. Common optical modeling techniques and...
Modeling and Simulation of Fiber Image Guide Multi-Chip Modules for MOEMS Applications (2008)
Steven P. Levitan, Timothy P. Kurzweg, Jose A. Martinez, Mark Kahrs, Jason Bakos, Jason Boles, ...
Densely integrated systems in the future will incorporate device and communication technologies that span the domains of digital and analog electronics, optics, micro-mechanics, and micro-fluidics....
Temporal Speci cation Veri cation via Causal Reasoning LIMITED DISTRIBUTION NOTICE (2008)
Alan R. Martello, Steven P. Levitan
This report has been, or will be, submitted for publication outside of the University of Pittsburgh and will probably be copyrighted if accepted for publication. It has been issued as a Technical...
Efficient Optical Communications Using Multi-Bit Differential Signaling (2008)
Donald M. Chiarulli, Steven P. Levitan, Samuel J. Dickerson, Jason D. Bakos, Joel Martin
We present an alternative signaling method for multi-channel fiber ribbon based optical links. The method is based on a hybrid of differential signaling and single-ended channels. Channels are...
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I DD switching transients on the supply rails. We show...
Abstract Digital Integrated Circuit Testing using Transient Signal Analysis (2008)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of I DD switching transients on the supply rails and voltage transients at selected test points. We present...
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I DD switching transients on the supply rails. We show...
Yee-wing Hsieh, Steven P. Levitan
We present new non-deterministic finite state machine (NFSM) abstraction techniques for comparators based on the comparison difference of the two operands (e.g., counters) instead of the comparison...
Temporal Specification Verification via Causal Reasoning (2007)
Alan R. Martello, Steven P. Levitan
We present a technique for verifying the timing specifications of the interfaces between digital systems. The verification process takes as input the timing protocols of each component as well as the...
Modeling and simulating optical MEMS using Chatoyant (2007)
Timothy P. Kurzweg, Steven P. Levitan, Philippe J. Marchand, Jose A. Martinez, Kurt R. Prough, Donald M. Chiarulli
The use of MEMs technology has enabled the fabrication of micro-optical and micro-electro-mechanical systems on a common substrate. This has led to new challenges in computer aided design of optical...
Enhancing The Performance Of Presumed Commit Protocol (2007)
Panos K. Chrysanthis, Steven P. Levitan
This paper presents a new read-only optimization called the unsolicited update--vote that when combined with the presumed commit protocol (PrC), eliminates all the logging activities from PrC for...
Congestion Router for Schematic Diagrams (2007)
Stephen T. Frezza, Steven P. Levitan
This paper presents a new approach to routing schematic diagrams. Heuristic global and local algorithms are presented which focus on congestion and crossover issues in the development of...
A Fast Optical Propagation Technique for Modeling MicroOptical Systems (2007)
Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, Donald M. Chiarulli
As designers become more aggressive in introducing optical components to micro-systems, rigorous optical models are required for system-level simulation tools. Common optical modeling techniques and...
Abstract Defect Detection Using Regression Analysis of Transient Signal Data (2007)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage tran-sients at multiple test points and on I DD switching transients on the supply rails. We show...
1 Defect Detection Using Regression Analysis of Transient Signal Data (2007)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I DD switching transients on the supply rails. We show...
FOR MULTI-BIT DIFFERENTIAL CHANNELS (2005)
Jason D. Bakos, Jason D. Bakos, Donald M. Chiarulli, Bruce R. Childers, Steven P. Levitan, Patchrawat Uthaisombut, ...
This dissertation was presented by
Active Substrates for Optoelectronic Interconnect (2004)
Donald M. Chiarulli, Jason Bakos, Steven P. Levitan, Charles Kuznia
We present the design of an intelligent optoelectronic chip carrier (IOCC). This is an active package that is the basis for short haul, PCB[1] and MCM[2,3] level, optical interconnect. Our goal is a...
Lightweight Hierarchical Error Control Codes for Multi-Bit Differential Channels (2004)
Jason D. Bakos, Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, Bruce R. Childers, Patchrawat Uthaisombut, ...
This proposal was presented by
Optoelectronic Multi-Chip-Module Implementation of a 64-Channel Fiber Switch (2002)
Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan
We present a demonstration prototype of an optoelectronic 3-chip OE-MCM module that implements a 64-channel non-blocking fiber optic switch. Each OE-switch-chip was implemented using Peregrine UTSI...
A flexible datapath allocation method for architectural synthesis (1999)
Kyumyung Choi, Steven P. Levitan
for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or...
Nfsm generation for semantics based model abstraction (1999)
Yee-wing Hsieh, Steven P. Levitan
We present a method for abstracting nondeterministic nite state machine (NFSM) models from behavioral VHDL descriptions for formal veri cation. The method is based on semantic matching of the results...
A flexible datapath allocation method for architectural synthesis (1999)
We present a robust datapath allocation method that is flexible enough to handle constraints imposed by a variety of target architectures. Key features of this method are its ability to handle...
The Image Understanding Architecture Project. (1998)
Weems, Charles C., Levitan, Steven P., Hanson, Allen R., Riseman, Edward M., Shu, David B., Nash, J. G.
This report presents the results of the Image Understanding Architecture (IUA) project for the first year of its two-year contract period. The purpose of the IUA project is to design and construct a...
The Image Understanding Architecture Project. (1998)
Weems, Charles C., Levitan, Steven P., Hanson, Allen R., Riseman, Edward M., Shu, David
The primary goal of the Image Understanding Architecture (IUA) project is to build a proof-of-concept prototype of a 1/64th slice of a next generation vision architecture, and develop the software...
Parallel Memory Addressing Using Coincident Optical Pulses. (1998)
Chiarulli, Donald M., Melhem, Rami G., Levitan, Steven P.
This research was a preliminary investigation of the applicability of coincident optical pulse techniques to hybrid electronic-optical computing systems. The results of the investigation are focused...
Coincident Pulse Techniques for Hybrid Electronic Optical Computer Systems. (1998)
Chiarulli, Donald M., Melhem, Rami G., Levitan, Steven P.
This research was an investigation of the application of coincident pulse techniques to multiprocessor interconnection networks. The research focused on three main areas: an examination of the...
Coincident Pulse Techniques for Hybrid Electronic Optical Computer Systems. (1998)
Chiarulli, Donald M., Melhem, Rami G., Levitan, Steven P.
This research is an investigation of the application of coincident pulse techniques to multiprocessor interconnection networks. The research focuses on three main areas: an examination of the...
Optoelectronic Cache Memory System Architecture (1998)
Chiarulli, Donald M., Levitan, Steven P.
Under this contract, we have designed and implemented an optoelectronic cache memory and interface to a page oriented optical memory system. This work demonstrated that an optical memory can be...
Associative Memory Study: Architectures and Technology (1998)
Levitan, Steven P., Chiarulli, Donald M., Katsuri, Amirtha, Kettering, Joan
This report summarizes current work in technologies and architectures for associative or "content addressable" memory. Associative memory is better suited for several specific tasks such as database...
Low Level Signal Processing for the Optoelectronic Memory System Interface (1998)
Chiarulli, Donald M., Levitan, Steven P.
This report describes the development and implementation of channel coding and error detection firmware and software for a prototype optical memory system. Specific accomplishments include the...
Reconfigurable Processor Employing Optical Channels (1998)
Majd Sakr, Steven P. Levitan, C. Lee Giles, Donald M. Chiarulli
We describe a reconfigurable computing architecture that exploits parallel optical channels to support fast reconfiguration and compare our architecture to configuration cache based designs Keywords:...
Model Abstraction for Formal Verification (1998)
Yee-Wing Hsieh, Steven P. Levitan
As the complexity of circuit designs grows, designers look toward formal veri#cation to achieve better test coverage for validating complex designs. However, this approach is inherently...
Characterization of CMOS Defects using Transient Signal Analysis,” DFT (1998)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of defects. The...
Reconfigurable Opto/Electronic Multiprocessor Interconnection Structures. (1997)
Chiarulli, Donald M., Levitan, Steven P., Melhem, Rami G.
This research expended our previous research in communications, control and arbitration for optical fiber technology to multiprocessor multi-stage interconnection structures. In particular, have...
Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs (1997)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of voltage transients at multiple test points and I DD switching transients on the supply rails. We present...
Control/Data-flow Analysis for VHDL Semantic Extraction (1997)
Yee-wing Hsieh, Steven P. Levitan
Model abstraction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to the specifications to be verified....
Control / Data-flow Analysis for VHDL Semantic Extraction (1997)
Yee-wing Hsieh, Steven P. Levitan
this paper, we describe a method for extracting VHDL semantics for model abstraction to improve the performance of formal verification tools such as COSPAN. Keywords: VHDL semantics extraction,...
Model Abstraction for Formal Verification (1997)
Yee-wing Hsieh, Steven P. Levitan
As the complexity of circuit designs grows, designers look toward formal verification to achieve better test coverage for validating complex designs. However, this approach is inherently...
Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs (1997)
James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of voltage tran-sients at multiple test points and I DD switching transients on the supply rails. We...
Control/data-flow analysis for vhdl semantic extraction (1997)
Yee-wing Hsieh, Steven P. Levitan
Model abstraction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to the specifications to be verified....
Control/data- ow analysis for vhdl semantic extraction (1997)
Yee-wing Hsieh, Steven P. Levitan
Model abstraction reduces the number of states necessary to perform formal veri cation while maintaining the functionality of the original model with respect to the speci cations to be veri ed....
Performance of On-Line Learning Methods in Predicting Multiprocessor Memory Access Patterns (1996)
Sakr, Majd F., Levitan, Steven P., Chiarulli, Donald M., Horne, Bill G., Giles, C. Lee
Shared memory multiprocessors require reconfigurable interconnection networks (INs) for scalability. These INs are reconfigured by an IN control unit. However, these INs are often plagued by...
Performance of On-Line Learning Methods in Predicting Multiprocessor Memory Access Patterns (1996)
Sakr, Majd F., Levitan, Steven P., Chiarulli, Donald M., Horne, Bill G., Giles, C. Lee
Shared memory multiprocessors require reconfigurable interconnection networks (INs) for scalability. These INs are reconfigured by an IN control unit. However, these INs are often plagued by...
An Optoelectronic Cache Memory System Architecture (1996)
Donald Chiarulli, Steven P. Levitan
We present an investigation of the architecture of an optoelectronic cache which can integrate terabit optical memories with the electronic caches associated with high performance uni- and multi-...
Linking Requirements and Design Data for Automated Functional Evaluation (1996)
Steven P. Levitan, Panos K. Chrysanthis, Contact Person, Stephen Frezza, Stephen T. Frezza, Stephen T. Frezza
This paper presents a methodology for automating the evaluation of complex hierarchical designs using black-box testing techniques. Based on an exploration model for design, this methodology...
Majd Sakr, Steven P. Levitan, C. Lee Giles, Bill G. Horne, Marco Maggini, Donald M. Chiarulli
Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current...
Requirements-Based Design Evaluation (1995)
Stephen Frezza, Steven P. Levitan, Panos K. Chrysanthis
This paper presents a methodology for automating the evaluation of partial designs using black-box testing techniques. This methodology generates black-box evaluation tests using a novel semantic...
Donald M. Chiarulli, Steven P. Levitan, Rami P. Melhem, James P. Teza, Greg Gravenstreter
This paper presents a scalable electro-optical interconnection network architecture which is suitable for tightly coupled multiprocessors. The architecture is called a Partitioned Optical Passive...
Incorporating Interconnection Delays in VHDL Behavioral Synthesis (1993)
Yee-wing Hsieh, Steven P. Levitan, Barry M. Pangrle
Advances in VLSI technology have provided smaller feature sizes which allow the integration of large circuit designs into a single chip. As a result, the interconnection delay between functional...
SPAR: A Schematic Place And Route System (1993)
Stephen T. Frezza, Steven P. Levitan
This paper presents an approach to the automatic generation of schematic diagrams from circuit descriptions. The heuristics which make up the system are based on two principles of schematics...
A time domain approach for avoiding crosstalk (1993)
Chunming Qiao, Rami Georges Melhem, Donald M. Chiarulli, Steven P. Levitan
can he avoided by ensuring that a switch is not used by two connections simultaneously. In order to support crosstalk-free communications among N inputs and N outputs, a space domain approach dilates...
Incorporating interconnection delays in VHDL behavioral synthesis (1993)
Yee-wing Hsieh, Steven P. Levitan, Barry M. Pangrle
Advances in VLSI technology have provided smaller feature sizes which allow the integration of large circuit designs into a single chip. As a result, the interconnection delay between functional...
Demonstration of an All Optical Addressing Circuit, (1992)
Chiarulli, Donald M., Levitan, Steven P., Melhem, Rami G.
This experiment is based on two properties of optical signals, unidirectional propagation and predictable path delay. Using these properties, logic systems can be devised in which information is...
Library Based Synthesis System (1992)
Yee-wing Hsieh, Steven P. Levitan, Ph. D
Iwould especially like to thank Professor Steven Levitan for his guidance and patience throughout the development of this tool. I also would to thank Professor Barry Pangrle for his time in modifying...
An all optical addressing circuit: experimental results and scalability analysis (1991)
Donald M. Chiarulli, Robert M. Ditmore, Steven P. Levitan, Rami G. Melhem
Abstract-In this paper, we present results from a demon-stration of both single and parallel selection in a one of four optical addressing circuit operating at 250 MHz using coinci-dent pulse...
SPAR: A Schematic Place and Route System (1991)
Stephen Frezza, Steven P. Levitan
This paper presents an approach to the automatic generation of schematic diagrams from circuit descriptions. The heuristics which make up the system are based on two principles of schematics...
Using coincident optical pulses for parallel memory addressing (1987)
Donald M. Chiarulli, Rami G. Melhem, Steven P. Levitan
multiprocessors are the most widely used parallel processing architectures. Unfortunately, these systems suffer from a memory/bus bandwidth limitation problem. For thedesigner of a hybrid...
Architectural synthesis via vhdl (1526)
Steven P. Levitan, Yee-wing Hsieh, Alan R. Martello, Barry M. Pangrle
In this paper, we present results from our experiments integrating an architectural synthesis tool, SandS, into the Keystone VLSI design environment. The resulting Architectural VHDL Synthesis tool...
Diffractive Optical Propagation Techniques for Mixed-Signal CAD Tools
Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Philippe J. Marchand, Donald M. Chiarulli
Computer Aided Design (CAD) tools for modeling optical computing systems use a variety of different optical propagation techniques. However, for modeling micro-systems, common optical modeling...
Temporal Analysis of Time Bounded Digital Systems
Alan Martello And, Alan R. Martello, Steven P. Levitan
. To perform verification of digital systems with time bounded delays, it is essential to characterize the space of all possible system behaviors. In this paper, we describe our analysis technique...