Scaling Processors to 1 Billion Transistors and Beyond: IRAM (2007)
Stylianos Perissakis, Christoforos Kozyrakis, Tom Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, ...
this paper we introduce an alternative way of using the huge amount of real estate available on such a chip: integrating the processor and the main memory on the same die. We call this architecture...
Thesis (Ph. D. in Computer Science)--University of California, Berkeley, Spring 2000.
References Vectors and Streams (2000)
Lecturer Melvyn Lim, Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo Lopez, ...
Up to now, we have only looked at techniques that exploit instruction level parallelism to increase single-thread processor performance. The instruction level parallelism dictates how many...
Balancing Computation and Memory in High Capacity Reconfigurable Arrays (2000)
Stylianos Perissakis, Stylianos Perissakis, Stylianos Perissakis
Reconfigurable arrays have been used to speed up computational tasks, some times achieving orders of magnitude of improvement either in cost/performance or raw performance. An integral part of such...
Embedded DRAM for a Reconfigurable Array (1999)
Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, John Wawrzynek
A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be...
Embedded dram for a reconfigurable array (1999)
Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André Dehon, John Wawrzynek
A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be...
The Energy Efficiency of IRAM Architectures (1997)
Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce Mcgaughy, David Patterson, ...
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than...
Intelligent RAM (IRAM): The industrial setting, applications, and architectures (1997)
David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, ...
The goal of Intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include...
Scalable Processors in the Billion-Transistor Era: IRAM (1997)
Christoforos E. Kozyrakis, Stylianos Perissakis, David Patterson, Thomas Anderson, Krste Asanovic, Neal Cardwell, ...
ther architecture alternatives, like wide superscalar and VLIW (very long instruction word), suffer from drawbacks---implementation complexity, low utilization of resources, and immature compiler...
Scaling Processors to 1 Billion Transistors and Beyond: IRAM (1997)
Stylianos Perissakis, Christoforos E. Kozyrakis, Thomas Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, ...
Conventional architectures have been developed with a transistor budget of a few hundred thousand and have evolved to designs of about 10 million transistors, achieving impressive performance....
The energy efficiency of iram architectures (1997)
Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce Mcgaughy, David Patterson
recommended it as a promising area of research.
The Energy Efficiency of IRAM Architectures (1996)
Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce Mcgaughy, David Patterson, ...
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than...
Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures
David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, ...
The goal of Intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include...