Abstract On Switch Factor Based Analysis of Coupled RC Interconnects (2008)
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that the exact SF is a...
Abstract Noise Model for Multiple Segmented Coupled RC Interconnects (2008)
Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
Performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We present simple and improved analytical models for noise phenomena due to coupling capacitance. We...
Submitted to IEEE Trans. on CAD An Analytical Delay Model for RLC Interconnects (2008)
Andrew B. Kahng, Sudhakar Muddu
Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can...
Practical Approximation Algorithms for Separable Packing Linear Programs (2008)
Feodor F. Dragan, Andrew B. Kahn, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky, Er Zelikovsky
We describefVkw polynomial time approximation schemes fm generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Bu#er Blocks (GRBB). We extend...
Feodor F. Dragan, Andrew B. Kahng, Sudhakar Muddu, Er Zelikovsky
Abstract---To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in...
Noise Model for Multiple Segmented Coupled RC Interconnects (2007)
Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
Performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We present simple and improved analytical models for noise phenomena due to coupling capacitance. We...
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, ...
In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In...
New Analyses Of Distributed RC Interconnections (2007)
Andrew B. Kahng, Sudhakar Muddu
This paper gives new methods for calculating the time-domain response for a finite-length distributed RC line. We begin with the solution for diffusion in a semi-infinite distributed RC line [4, 12]...
Abstract On Switch Factor Based Analysis of Coupled RC Interconnects (2007)
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that the exact SF is a...
Delay Models for MCM Interconnects Under Monotone and Non-Monotone Response (2007)
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into...
Efficient Analyses and Models of VLSI and MCM Interconnects (2007)
Andrew B. Kahng, Sudhakar Muddu
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching methods used to model...
Feodor F. Dragan, Andrew B. Kahng, Ion I. M, Sudhakar Muddu, Alexander Zelikovsky
Abstract. We describe fully polynomial time approximation schemes for generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Buffer Blocks (GRBB). We extend...
Provably Good Global Buffering by Generalized Multiterminal Multicommodity Flow Approximation (2007)
Feodor F. Dragan, Andrew B. Kahng, Ion I. Măndoiu, Sudhakar Muddu, Alexander Zelikovsky
Abstract—To implement high-performance global interconnect without impacting the placement and per-formance of existing blocks, the use of buffer blocks is becoming increasingly popular in...
Provably good global buffering by multiterminal multicommodity flow approximation (2001)
Feodor F. Dragan, Andrew B. Kahng, Sudhakar Muddu, Er Zelikovsky
Abstract—To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in...
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroob, ...
In this paper, we describe optimization techniques to minimize important design objectives such as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we employ a new...
On Switch Factor Based Analysis of Coupled RC Interconnects (2000)
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that the exact SF is a...
Provably Good Global Buffering Using an Available Buffer Block Plan (2000)
Feodor F. Dragan, Andrew B. Kahng, Ion Mandoiu, Ion M, Alexander Zelikovsky, Sudhakar Muddu, ...
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC...
Provably Good Global Buffering Using an Available Buffer Block Plan (2000)
Feodor F. Dragan, Andrew B. Kahng, Ion Mandoiu, Sudhakar Muddu, Alexander Zelikovsky, Er Zelikovsky
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC...
Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs (1999)
Andrew Kahng Sudhakar, Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses,...
Noise and Delay Uncertainty Studies for Coupled RC Interconnects (1999)
Andrew B. Kahng, Sudhakar Muddu, Devendra Vidhani
The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of...
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization (1999)
Andrew B. Kahng, Sudhakar Muddu
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for...
Noise and Delay Estimation for Coupled RC Interconnects (1999)
Andrew Kahng, Sudhakar Muddu, Devendra Vidhani
The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We provide improved, easily computable estimates of crosstalk peak noise, as well as impact of...
Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs (1999)
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses,...
New Efficient Algorithms for Computing Effective Capacitance (1998)
Andrew B. Kahng, Sudhakar Muddu
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than previous methods for...
Interconnect Tuning Strategies for High-Performance ICs (1998)
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses,...
Interconnect Tuning Strategies for High-Performance ICs (1998)
Andrew Kahng Sudhakar, Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses,...
New efficient algorithms for computing effective capacitance (1998)
Andrew B. Kahng, Sudhakar Muddu
recent 0.25µm high-end microprocessor project confirm the accuracy of We describe a novel iterationless approach for computing the effective our new methods. capacitance of an interconnect load at a...
Andrew B. Kahng, Sudhakar Muddu
This paper gives new methods for calculating the time-domain response for a finite-length distributed RC line that is stimulated by a ramp input. The following are our contributions. First, we obtain...
Delay Models for MCM Interconnects When Response is Non-monotone (1997)
Andrew Kahng, Kei Masuko, Sudhakar Muddu
Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into...
Studies of Interconnect Tuning for High-Performance Designs (1997)
Andrew B. Kahng, Sudhakar Muddu, Rahul Sharma
Interconnect tuning is an increasingly critical degree of freedom in the design of high-performance VLSI systems. By interconnect tuning, we refer to the selection by a design team of line...
Andrew B. Kahng, Sudhakar Muddu
We present a general and, in the limit, exact approach to compute the time-domain response for finite-length RC lines under ramp input, by summing distinct diffusions starting at either end of the...
Efficient gate delay modeling for large interconnect loads (1996)
Andrew B. Kahng, Sudhakar Muddu
With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new \Pi model for...
Analytical Delay Models for VLSI Interconnects Under Ramp Input (1996)
Andrew B. Kahng, Sudhakar Muddu
Elmore delay has been widely used to estimate the interconnect delays in the performancedriven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can...
Analytical Delay Models for VLSI Interconnects Under Ramp Input (1996)
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
For typical RLC interconnections with ramp input as the source voltage, Elmore delay can deviate significantly (by up to 100 % or more) from SPICE-computed delay since it is independent of rise time...
Max-Min Rate Control Algorithm for Available Bit Rate Service in ATM Networks (1996)
Sudhakar Muddu, Christos Tryfonas, Fabio M. Chiussi, Vijay P. Kumar
The definition of Available Bit Rate (ABR) service has been the focus of the recent activities of the ATM Forum. The Forum has adopted rate-based schemes as the standard for congestion control of ABR...
Efficient Gate Delay Modeling for Large Interconnect Loads (1996)
With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new P model for...
An Analytical Delay Model for RLC Interconnects (1996)
Andrew B. Kahng, Sudhakar Muddu
Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can...
Analysis of RC Interconnections under Ramp Input (1996)
Andrew B. Kahng, Sudhakar Muddu
We present a general and, in the limit, exact approach to compute the time-domain response for finite-length RC lines under ramp input, by summing distinct diffusions starting at either end of the...
Analytical Delay Models for VLSI Interconnects under Ramp Input (1996)
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However, for typical RLC...
An Analytical Delay Model for RLC Interconnects (1996)
Andrew B. Kahng, Sudhakar Muddu
We develop an analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines. Delay estimates using our analytical model...
Gate Load Delay Computation Using Analytical Models (1996)
With submicron technologies, gate delays are dominated by gate load delays rather than intrinsic gate delays. While the common approach for computing gate load delay (or total gate delay) is through...
Delay Analysis of Coupled Transmission Lines (1996)
In this paper, we analyze coupled transmission lines and obtain a relationship between the moments of the coupled transfer functions. We then derive expressions for the first and second moments of...
Analysis of RC Interconnections under Ramp Input (1996)
Andrew B. Kahng, Sudhakar Muddu
, ramp input response, VLSI interconnects 1. INTRODUCTION Estimating delays on VLSI interconnections is a key element in timing verification, gate-level simulation and performance-driven layout...
Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments (1994)
Andrew B. Kahng, Sudhakar Muddu
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, or moment...
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (1994)
The traditional analysis of signal delay in a transmission line begins with a lossless LC representation, which yields a wave equation governing the system response; 2-port parameters are typically...