This subclass of the RISC processors allow multiple instructoins to be issued simultaneously during each cycle. The effective CPI of a superscalar processor should be less than that of a generic...
1 Reservation Station Architecture for Mutable Functional Unit Usage in (2007)
Superscalar Processors, Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
One major bottleneck of a superscalar processor is mismatch of instruction stream mix with functional unit configuration. Depending on the type and number of functional units, the performance loss...
Superscalar Processors, Ben Lee
The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support....
Evaluation of Alternative Data Speculation Approaches for Superscalar Processors (1997)
José González, Antonio González, Superscalar Processors
Data dependences are one of the main limits to the amount of ILP that current processors can exploit. Data speculation are becoming a promising mechanism to avoid the ordering imposed by data...