An Area-Efficient GF(2 m) MSD Multiplier based on an MSB Multiplier for Elliptic Curve LSI (2008)
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Abstract: In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2 m). The proposed multiplier is based on connecting D (digit...
A Secure Test Technique for Pipelined Advanced Encryption Standard (2008)
SHI, Youhua, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo
In this paper, we presented a Design-for-Secure-Test (DFST) technique for pipelined AES to guarantee both the security and the test quality during testing. Unlike previous works, the proposed method...
SHI, Youhua, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo
This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for...
Kohara, Shunitsu, Tomono, Naoki, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction (2006)
Shi, Youhua, Togawa, Nozomu, Kimura, Shinji, Yanagisawa, Masao, Ohtsuki, Tatsuo
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (2006)
Jumpei Uchida †a, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
SUMMARY Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm...
FCSCAN: An efficient multiscan-based test compression technique for test cost reduction (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
Abstract — This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of...
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (2006)
UCHIDA, Jumpei, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo
Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem...
SHI, Youhua, TOGAWA, Nozomu, KIMURA, Shinji, YANAGISAWA, Masao, OHTSUKI, Tatsuo
This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel...
A Processor Core Synthesis System in IP-based SoC Design (2005)
Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
A Processor Core Synthesis System in IP-based SoC Design (2005)
Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis (2005)
KAWAZU, Hideki, UCHIDA, Jumpei, MIYAOKA, Yuichiro, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo
A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k × n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor...
TOGAWA, Nozomu, TACHIKAKE, Koichi, MIYAOKA, Yuichiro, YANAGISAWA, Masao, OHTSUKI, Tatsuo
This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm...
A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)
Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo
Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning (2004)
Uchida, Jumpei, Mkiyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)
Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo
Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning (2004)
Uchida, Junpei, Mkiyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
An Efficient Algorithm/Architecture Codesign for Image Encoders (2004)
Choi, Jinku, Togawa, Nozomu, Ikenaga, Takeshi, Goto, Satoshi, Yanagisawa, Masao, Ohtsuki, Tatsuo
An Efficient Algorithm/Architecture Codesign for Image Encoders (2004)
Choi, Jinku, Togawa, Nozomu, Ikenaga, Takeshi, Goto, Satoshi, Yanagisawa, Masao, Ohtsuki, Tatsuo
A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths (2004)
Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Instruction Set and Functional Unit Synthesis for SIMD Processor Cores (2004)
Togawa, Nozomu, Tachikake, Koichi, Miyaoka, Yuichiro, Yanagisawa, Masao, Ohtsuki, Tatsuo
A hardware/software partitioning algorithm for SIMD processor cores (2003)
Tachikake, Koichi, Miyaoka, Yuichiro, Choi, Jinku, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
A hardware/software partitioning algorithm for SIMD processor cores (2003)
Tachikake, Koichi, Miyaoka, Yuichiro, Choi, Jinku, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Under the Supervision of (2002)
Jinku Choi, Prof Dr, Tatsuo Ohtsuki, Copyright Jinku Choi
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