Non-uniform Selective Way Cache の動的制御による組込みプロセッサの省エネルギー化 (2009)
石飛, 百合子, 石原, 亨, 安浦, 寛人, Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, ...
本稿はNon-uniform Selective Way Cache(NSWC) の動的ウェイ切り替えによる組込みプロセッサの省エネルギー化手法の提案を行う．NSWC...
シングルサイクルアクセス可能な二階層キャッシュアーキテクチャ (2009)
山口, 誠一朗, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, Ishihara, Tohru, Yasuura, Hiroto, ...
組込みプロセッサのメモリサブシステムの消費エネルギーを削減するために，プロセッサコアとL1キャッシュメモリ（以下，キャッシュメモリを単に...
Abstract Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption (2009)
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of...
This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of Most Recently Used (MRU) addresses...
Energy-Efficient Embedded System Design at 90nm and Below – A System-Level Perspective – (2008)
Abstract. Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. This paper presents our recent research activities and...
A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems (2008)
Zeng, Gang, Tomiyama, Hiroyuki, Takada, Hiroaki, Ishihara, Tohru
A generalized dynamic energy performance scaling (DEPS) framework is proposed for exploring application-specific energy-saving potential in hard real-time embedded systems. This software-centric...
Yamaguchi, Seiichiro, Ishihara, Tohru, Yasuura, Hiroto, 山口, 誠一朗, 石原, 亨, 安浦, 寛人, ...
International SoC Design Conference (ISOCC 2008) : November 24-25, 2008 : Busan, Korea
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories (2008)
Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, 石飛, 百合子, 石原, 亨, 安浦, 寛人, ...
This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and...
キャッシュウェイ割当てとコード配置最適化による組込みプロセッサの省エネルギー化 (2008)
石飛, 百合子, 石原, 亨, 安浦, 寛人, Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, ...
DAシンポジウム2008-システムLSI設計技術とDA－ : 2008年8月26日(火)-27日(水) : 静岡
コード配置とメモリ構成の同時最適化による省電力化手法 (2008)
松村, 忠幸, 石原, 亨, 安浦, 寛人, Matsumura, Tadayuki, Ishihara, Tohru, Yasuura, Hiroto, ...
DAシンポジウム2008-システムLSI設計技術とDA－ : 2008年8月26日(火)-27日(水) : 静岡
組込みシステムの消費エネルギー削減を目的とした不均一キャッシュアーキテクチャ (2008)
山口, 誠一朗, 石飛, 百合子, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, ...
DAシンポジウム2008 : システムLSI設計技術とDA : 2008年8月26日(火)-27日(水) : 静岡
Chapter 6 ENERGY MANAGEMENT TECHNIQUES FOR SOC DESIGN (2008)
Hiroto Yasuura, Tohru Ishihara, Masanori Muroyama
Abstract: One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in...
Row/Column Redundancy to Reduce SRAM Leakage in Presence of Random Within-Die Delay Variation (2008)
Goudarzi, Maziar, Ishihara, Tohru, 石原, 亨, イシハラ, トオル
International Symposium on Low Power Electronics and Design 2008 : Bangalore, India : August 11-13, 2008
Goudarzi, Maziar, Ishihara, Tohru, 石原, 亨, イシハラ, トオル
Great Lakes Symposium on VLSI (GLSVLSI) 2008 : May 4-6, 2008 : Orlando, Florida
Matsumura, Tadayuki, Ishihara, Tohru, Yasuura, Hiroto, 松村, 忠幸, 石原, 亨, 安浦, 寛人, ...
The 18th ACM Great Lakes symposium on VLSI : May 04-06, 2008 : Orlando, Florida, USA
石原, 亨, Ishihara, Tohru, イシハラ, トオル
第21回 回路とシステム軽井沢ワークショップ : 2008年4月21日-22日 : 軽井沢
Cache Power Reduction in Presence of Within-Die Delay Variation using Spare Ways (2008)
Goudarzi, Maziar, Matsumura, Tadayuki, Ishihara, Tohru, 松村, 忠幸, 石原, 亨, マツムラ, タダユキ, ...
IEEE Computer Society Annual Symposium on VLSI : April 7-9, 2008 : Montpellier, France
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems (2008)
Sugihara, Makoto, Ishihara, Tohru, Murakami, Kazuaki, 杉原, 真, 石原, 亨, 村上, 和彰, ...
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of...
Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems (2008)
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable...
負荷変動に瞬時適応可能なマルチパフォーマンスプロセッサの設計と評価 (2008)
山口, 誠一朗, 大山, 裕一郎, 国武, 勇次, 松村, 忠幸, 石飛, 百合子, 山口, 聖貴, ...
動的可変電圧プロセッサ（以下DVSプロセッサ）の代用となるマルチパフォーマンスプロセッサについて述べる．マルチパフォーマンスプロセッサは...
Energy-Efficient Embedded System Design at 90nm and Below : A System-Level Perspective (2008)
Ishihara, Tohru, 石原, 亨, イシハラ, トオル
High-Performance Computing : 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers
Goudarzi, Maziar, Ishihara, Tohru, Noori, Hamid, 石原, 亨, イシハラ, トオル
High Performance Embedded Architectures and Compilers : Third International Conference, HiPEAC 2008 : January 27-29, 2008 : Göteborg, Sweden
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems (2008)
SUGIHARA, Makoto, ISHIHARA, Tohru, MURAKAMI, Kazuaki
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of...
Way-Scaling to Reduce Power of Cache with Delay Variation (2008)
GOUDARZI, Maziar, MATSUMURA, Tadayuki, ISHIHARA, Tohru
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistors improves leakage,...
A Power Minimization Technique for Arithmetic Circuits by Cell Selection (2007)
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper...
Tohru Ishihara, Student Member, Hiroto Yasuura
er, a novelap98AC08E9 sp ecificp ower op=%9=C08E9 technique utilizing small instruction ROM which is pC%= % between an instruction cache or a mainpnC%G9 memory and PU core ispCG osed. OuropG9897C0AB...
製造後にタイミング補正可能なオンチップバスアーキテクチャ (2007)
山口, 聖貴, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Masaki, Muroyama, Masanori, ...
デザインガイア2007 -VLSI設計の新しい大地を考える研究会- : Design Gaia 2007 -A New Frontier in VLSI Design- : 2007.11.20～22 : 北九州国際会議場
組込みプロセッサのエネルギー消費を最小化するコード配置最適化問題のILPモデル (2007)
石飛, 百合子, 石原, 亨, 安浦, 寛人, Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, ...
本稿では，CPU...
マルチタスク組込みアプリケーションの低消費エネルギー化のためのメモリ管理技術 (2007)
山口, 誠一朗, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, Muroyama, Masanori, ...
携帯情報機器をはじめとした組込みシステムではメモリ・システムのエネルギー削減が強く求められている．キャッシュ・メモリよりもアクセスに...
A Hybrid Memory Architecture for Low Power Embedded System Design (2007)
Matsumura, Tadayuki, Ishitobi, Yuriko, Ishihara, Tohru, Goudarzi, Maziar, Yasuura, Hiroto, 松村, 忠幸, ...
The 14th Workshop on Synthesis And System Integration of Mixed Information technologies : SASIMI 2007 : October 15(Mon)-16(Tue), 2007 : Hokkaido, Japan
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems (2007)
SUGIHARA, Makoto, ISHIHARA, Tohru, MURAKAMI, Kazuaki
This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error...
Goudarzi, Maziar, Matsumura, Tadayuki, Ishihara, Tohru, 松村, 忠幸, 石原, 亨, マツムラ, タダユキ, ...
4th International Workshop on Dependable Embedded Systems : October 9, 2007 : Beijing, China
Ishihara, Tohru, Goudarzi, Maziar, 石原, 亨, イシハラ, トオル
International SoC Design Conference : October 15-16 : Korea
コード配置変更によるハイブリッドローカルメモリの消費エネルギー最小化 (2007)
松村, 忠幸, 石飛, 百合子, 石原, 亨, 安浦, 寛人, Matsumura, Tadayuki, Ishitobi, Yuriko, ...
本稿ではハイブリッドメモリの有効利用によるオンチップメモリの消費エネルギー削減手法を提案する．ハイブリッドメモリは次の二つの領域で構...
組込みシステムの低消費エネルギー化を目的としたコード配置最適化とそのILPモデルの提案 (2007)
石飛, 百合子, 石原, 亨, 安浦, 寛人, Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, ...
第60回電気関係学会九州支部連合大会 : 平成19年9月18日(火)～19日(水) : 琉球大学(沖縄)
小容量オンチップメモリの有効利用による組込みシステムの低消費エネルギー化 (2007)
山口, 誠一朗, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, Muroyama, Masanori, ...
第60回電気関係学会九州支部連合大会 : 平成19年9月18日(火)～19日(水) : 琉球大学(沖縄)
製造後に性能補償可能なオンチップバスアーキテクチャ (2007)
山口, 聖貴, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Masaki, Muroyama, Masanori, ...
スクラッチパッドメモリを考慮したコード配置最適化による組込みシステムの低消費エネルギー化 (2007)
石飛, 百合子, 石原, 亨, 安浦, 寛人, Ishitobi, Yuriko, Ishihara, Tohru, Yasuura, Hiroto, ...
DAシンポジウム2007(システムLSI設計技術とDA) : 2007年8月29日(水)～30日(木) : 静岡
A Multi-Performance Processor for Low Power Embedded Applications (2007)
Oyama, Yuichiro, Ishihara, Tohru, Sato, Toshinori, Yasuura, Hiroto, 石原, 亨, 佐藤, 寿倫, ...
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The major advantage over the...
プロセスばらつきを考慮したSRAMセルの低消費電力設計手法 (2007)
松村, 忠幸, 室山, 真徳, 石原, 亨, 安浦, 寛人, Matsumura, Tadayuki, Muroyama, Masanori, ...
2007電子情報通信学会総合大会 : 2007年3月20日(火)～23日(金) : 名古屋 : AS-3-1
プロセッサベース組込みシステムの低消費電力化を目的としたクロックゲーティング命令に関する検討 (2007)
山口, 誠一朗, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, Muroyama, Masanori, ...
2007電子情報通信学会総合大会 : 2007年3月20日(火)～23日(金) : 名古屋 : A-3-18
90nmCMOS回路における遅延・電力ばらつきのゲート段数およびゲート幅依存性に関する考察 (2007)
山口, 聖貴, Yang, Yuan, 坂本, 良太, 室山, 真徳, 石原, 亨, 安浦, 寛人, ...
近年，製造ばらつきに起因する回路性能のばらつきが顕著になってきている．回路性能のばらつきは歩留まりを低下させるため，ばらつきに対処す...
CMOS回路におけるタイミング歩留り最大化のためのゲートサイジング手法の提案 (2007)
坂本, 良太, 室山, 真徳, 石原, 亨, 安浦, 寛人, Sakamoto, Ryota, Muroyama, Masanori, ...
半導体微細加工技術の進歩により，製造ばらつきによるチップの性能歩留り低下が問題となっている．従来から，回路の平均遅延時間を最小にする...
いまさら聞けない低消費 : 教えます。現場で使える低消費設計 (2007)
石原, 亨, Ishihara, Tohru, イシハラ, トオル
Electronic Design and Solution Fair 2008(EDSFair2008) : 2007年1月24日, 25日 : パシフィコ横浜, 神奈川
Variation Aware Compilation for Improving Energy-Efficiency of Nanometer Processor Caches (2006)
Goudarzi, Maziar, Ishihara, Tohru, Yasuura, Hiroto, 石原, 亨, 安浦, 寛人, イシハラ, トオル, ...
Workshop on Compiler Assisted SoC Assembly (CASA2006) : Seoul, South Korea
An Energy Characterization Framework for Software-Based Embedded Systems (2006)
Lee, Donghoon, Ishihara, Tohru, Muroyama, Masanori, Yasuura, Hiroto, Fallah, Farzan, 李, 東勲, ...
Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2006) : 2006年10月26日～27日：Seoul, South Korea
Energy Management Techniques for SoC Design (2006)
Yasuura, Hiroto, Ishihara, Tohru, Muroyama, Masanori, 安浦, 寛人, 石原, 亨, 室山, 真徳
One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design...
90nmCMOS回路における遅延および電力ばらつきの実測と解析 (2006)
山口, 聖貴, Yang, Yuan, 樽見, 幸祐, 坂本, 良太, 室山, 真徳, 石原, 亨, ...
近年，製造ばらつきに起因する回路性能のばらつきが顕著になってきている．回路性能のばらつきによっ...
Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design (2006)
Yamaguchi, Seiichiro, Muroyama, Masanori, Ishihara, Tohru, Yasuura, Hiroto, 山口, 誠一朗, 室山, 真徳, ...
This paper proposes a low power software design technique for processor-based embedded systems. A basic idea is to reduce switching activities in sign extension bits of instruction operands through...
オペランドのビット幅を考慮したソフトウェアレベル消費エネルギー削減手法 (2006)
山口, 誠一朗, 室山, 真徳, 石原, 亨, 安浦, 寛人, Yamaguchi, Seiichiro, Muroyama, Masanori, ...
本稿では，マイクロプロセッサベース組込みシステムのソフトウェアレベル消費エネルギー削減手法を提...
Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Optimization (2006)
Yamaguchi, Seiichiro, Muroyama, Masanori, Ishihara, Tohru, Yasuura, Hiroto, 山口, 誠一朗, 室山, 真徳, ...
Proceedings of the International PhD Student Workshop on SOC, Jul. 2006.
マイクロプロセッサのエネルギー消費特性抽出とソフトウェアデバッガを用いた消費エネルギー見積もり (2006)
李, 東勲, 石原, 亨, 室山, 真徳, 安浦, 寛人, Fallah, Farzan, Lee, Donghoon, ...
マイクロプロセッサの消費エネルギーを高い抽象度でキャラクタライズする手法を提案する。消費エネルギーのモデルには線形式を用いる。本稿に...
A Simulation-Based Soft Error Estimation Methodology for Computer Systems (2006)
Sugihara, Makoto, Ishihara, Tohru, Hashimoto, Koji, Muroyama, Masanori, 杉原, 真, 石原, 亨, ...
This paper proposes a simulation-based soft error estimation methodology for computer systems. Accumulating soft error rates (SERs) of all memories in a computer system results in pessimistic soft...
An Energy Characterization Framework for Software-Based Embedded Systems (2006)
Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
Abstract — This paper proposes an energy characterization framework which helps designers in developing a fast and accurate energy model for a target processor-based system. We use a linear model...
A Cache-Defect-Aware Code Placement Algorithm for Improving the Performance of Processors (2005)
Ishihara, Tohru, Fallah, Farzan, 石原, 亨, ファラー, ファーザン
Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that faultfree sections can...
石原, 亨, 冨山, 宏之, Ishihara, Tohru, Tomiyama, Hiroyuki
Power consumption has been a critical issue in the embedded system design. However, embedded software has been traditionally designed without taking care of the power consumption issues. This paper...
プログラムの動作を考慮したコンピュータシステムのソフトエラー数見積もり技術 (2005)
杉原, 真, 石原, 亨, 橋本, 浩二, 室山, 真徳, Sugihara, Makoto, Ishihara, Tohru, ...
集積回路の加工寸法の縮小に伴い，回路の動作電圧とノイズマージンが低下し，宇宙線に起因するソフト...
マイクロプロセッサの性能歩留まりを改善する命令コード配置手法 (2005)
石原, 亨, Fallah, Farzan, Ishihara, Tohru, ファラー, ファーザン
製造上の欠陥を含むチップであっても、欠陥箇所がチップの機能に影響を与えないように無効化することにより良品チップとして使用することがで...
A Non-Uniform Cache Architecture for Low Power System Design (2005)
Ishihara, Tohru, Fallah, Farzan, 石原, 亨, ファラー, ファーザン
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e., the number of...
Ishihara, Tohru, Fallah, Farzan
This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of Most Recently Used (MRU) addresses...
Ishihara, Tohru, Fallah, Farzan
This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of Most Recently Used (MRU) addresses...
A non-uniform cache architecture for low power system design (2005)
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e., the number of...
A Power Minimization Technique for Arithmetic Circuits by Cell Selection (2002)
Muroyama, Masanori, Ishihara, Tohru, Hyodo, Akihiko, Yasuura, Hiroto, 室山, 真徳, 石原, 亨, ...
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper...
入力信号パターンを考慮した低電力算術演算回路の設計手法 (2001)
室山, 真徳, 石原, 亨, 兵頭, 章彦, 安浦, 寛人, Muroyama, Masanori, Ishihara, Tohru, ...
算術演算器はマイクロプロセッサをはじめ，画像処理などの様々なLSI の重要な構成要素である．ディジタル信号処理プロセッサ（DSP）や動画像...
DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ (2001)
井上, 弘士, 石原, 亨, 甲斐, 康司, 村上, 和彰, Inoue, Koji, Ishihara, Tohru, ...
DRAMとロジックの混載は,...
Software energy reduction techniques for variable-voltage processors (2001)
Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
A processor consumes far less energy running tasks requiring a low supply voltage than it does executing high-performance tasks. Effective voltage-scheduling techniques take advantage of this...
室山, 真徳, 石原, 亨, 兵頭, 章彦, 安浦, 寛人, Muroyama, Masanori, Ishihara, Tohru, ...
入力信号パターンを考慮した低電力並列乗算器の設計手法 (2000)
室山, 真徳, 石原, 亨, 兵頭, 章彦, 安浦, 寛人, Muroyama, Masanori, Ishihara, Tohru, ...
DAシンポジウム2000 : 2000年7月17日(月)～19日(水) : 静岡
Tohru Ishihara, Hiroto Yasuura
Abstract — In this paper, a power reduction technique which merges frequently executed sequences of object codes into a set of single instructions is proposed. The merged sequence of object codes...
Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption (1999)
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of...
可変電源電圧プロセッサに対するリアルタイムタスクスケジューリング手法 (1998)
大隈, 孝憲, 石原, 亨, 安浦, 寛人, Okuma, Takanori, Ishihara, Tohru, Yasuura, Hiroto, ...
動的に電源電圧を変化させ,...
Voltage scheduling problem for dynamically variable voltage processors (1998)
Tohru Ishihara, Hiroto Yasuura
This paper presents a model of dynamically variable voltage processor and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and formulated as an...
Power-Pro: Programmable Power Management Architecture (1998)
Tohru Ishihara, Hiroto Yasuura, Programmable Power Management
This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. Power-Pro architecture has following two functionalities,...
Programmable Power Management Architecture for Power Reduction (1998)
Tohru Ishihara, Hiroto Yasuura
This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities :...
Voltage Scheduling Problem for Dynamically Variable Voltage Processors (1998)
Tohru Ishihara, Hiroto Yasuura
This paper presents a model of dynamically variable voltage processor and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and formulated as an...
Instruction Scheduling for Power Reduction in Processor-Based System Design (1998)
Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
This paper propose an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main...
Optimization of Supply Voltage Assignment for Power Reduction on Processor-Based Systems (1997)
Tohru Ishihara, Hiroto Yasuura
In this paper we propose a system level power optimization problem : A problem to assign optimal VDD to each job under a time constraint. The objective function is total energy for the processing of...
Purification and Characterization of Polyamine Aminotransferase of Arthrobacter sp. TMP-1 (1997)
Yorifuji, Takamitsu, Ishihara, Tohru, Naka, Takashi, Kondo, Shinya, Shimizu, Eiichi
Polyamine aminotransferase of Arthrobacter sp. TMP-1 was induced by 1,3-diaminopro-pane (DAP), N-3-aminopropyl-1,3-diaminopropane (norspermidine), spermidine, and spennine, but not by putrescine. The...
Action of Polyamine Aminotransferase on Norspermidine (1997)
Yorifuji, Takamitsu, Kondo, Shinya, Naka, Takashi, Ishihara, Tohru, Shimizu, Eiichi
The norspermidine-pyruvate reaction catalyzed by polyamine aminotransferase from Arthrobacter sp. TMP-1 formed N-3-aminopropyl-3-aminopropionaldehyde (APAPAL), L-alanine, 1,3-diaminopropane (DAP),...
Basic Experimentation on Accuracy of Power Estimation for CMOS VLSI Circuits (1996)
Tohru Ishihara, Hiroto Yasuura
In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits...
Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits (1996)
Tohru Ishihara, Hiroto Yasuura
this paper, we discuss on accuracy of power dissipation models for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits [1][2][3][4]....