Junji Yamamoto, Takashi Fujiwara, Takuji Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
interconnection network architecture
Toshihiro Hanawa, Takashi Fujiwara, Hideharu Amano
Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure /control, and permits the...
Akira Funahashi, Toshihiro Hanawa, Hideharu Amano
this paper, a fault recovery mechanism is attached to these two networks, and proposed Fault tolerant TBSF (F-TBSF) and Fault tolerant PBSF (FPBSF) respectively. Then, the performance degradation...
The MINC(Multistage Interconnection Network with Cache control mechanism) chip (2007)
Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
Introduction Although bus connected multiprocessors have been widely used as high-end workstations or servers, the number of connected processors is strictly limited by the maximum bandwidth of the...
The MINC chip: Multistage Interconnection Network with Cache control mechanism chip (2007)
Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano
The Multistage Interconnection Network with Cache control mechanism (MINC) is a hardware mechanism to control the cache coherent in a switchconnected multiprocessors using a crossbar or Multistage...
MINC: Multistage Interconnection Network with Cache control mechanism (1997)
Control Mechanism, Toshihiro Hanawa, Takayuki Kamei, Hideki Yasukawa, Katsunobu Nishimura, ...
this paper.
Multistage Interconnection Networks with multiple outlets (1994)
Toshihiro Hanawa, Hideharu Amanoy, Yoshifumi Fujikawa
Abstract: Multistage Interconnection Networks(MINs) with multiple outlets are networks which can support higher bandwidth than that of nonblocking networks by passing multiple packets to the same...