Profile-directed speculative optimization of reconfigurable floating point data paths (2009)
Abstract. This paper presents a methodology for generating floatingpoint arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining...
AN ANALYTICAL MODEL DESCRIBING THE RELATIONSHIPS BETWEEN LOGIC ARCHITECTURE AND FPGA DENSITY (2009)
Andrew Lam, Philip Leong, Wayne Luk
This paper describes an analytical model, based principally on Rent’s Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the model relates the...
RAPID ESTIMATION OF POWER CONSUMPTION FOR HYBRID FPGAS (2009)
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA...
Floating Point FPGA: Architecture and Modelling (2009)
Chun Hok Ho, Chi Wai Yu, Philip Leong, Wayne Luk
Abstract—This paper presents an architecture for a reconfigurable device which is specifically optimised for floating point applications. Fine-grained units are used for implementing control logic...
Chi Wai Yu, Julien Lamoureux, Wayne Luk
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
SoftSONIC: A Customisable Modular Platform for Video Applications (2009)
Abstract. This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application development by raising the level of abstraction and facilitating design...
Dong-u Lee, John D. Villasenor, Wayne Luk
Abstract — We present the design and implementation of a Gaussian random number generator (GRNG) via hierarchical segmentation. Gaussian samples are generated using the inversion method, which...
DOMAIN-SPECIFIC HYBRID FPGA: ARCHITECTURE AND FLOATING POINT APPLICATIONS (2009)
Chun Hok Ho, Chi Wai Yu, Wayne Luk
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient...
Wayne Luk, Guanglie Zhang, John D. Villasenor
We show that the short period of the uniform random number generator in the published implementation of Marsaglia and Tsang’s Ziggurat method for generating random deviates can lead to poor...
Perspectives on Custom Computing (2009)
Custom computing involves customising computations for one or more applications in a given implementation technology. We describe a framework for customising designs using appropriate libraries,...
Accelerating Seismic Computations Using Customized Number Representations on FPGAs (2009)
Haohuan Fu, William Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk
The oil and gas industry has an increasingly large demand for high-performance computation over huge volume of data. Compared to common processors, field-programable gate arrays (FPGAs) can boost the...
Chi Wai Yu, Julien Lamoureux, Wayne Luk
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
Accelerating Seismic Computations Using Customized Number Representations on FPGAs (2009)
Haohuan Fu, William Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk
The oil and gas industry has an increasingly large demand for high-performance computation over huge volume of data. Compared to common processors, field-programable gate arrays (FPGAs) can boost the...
Run-Time Integration of Reconfigurable Video Processing Systems (2008)
Pete Sedcole, Senior Member, George A. Constantinides, Wayne Luk
Abstract—Embedded systems in field-programmable gate arrays (FPGAs) can be customized and adaptive if assembled from modular components at run time. This paper examines realizing run-time system...
DOMAIN-SPECIFIC HYBRID FPGA: ARCHITECTURE AND FLOATING POINT APPLICATIONS (2008)
Chun Hok Ho, Chi Wai Yu, Wayne Luk
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient...
Scalable Acceleration of Inductive Logic Programs (2008)
Andreas Fidjel, Wayne Luk, Stephen Muggleton
Inductive logic programming systems are recognised as an emerging but powerful paradigm for machine learning which can make use of background knowledge to produce theories expressed in logic. They...
Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints (2008)
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can Özturan
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formulation, that...
Theerayod Wiangtong, Wayne Luk
[A systematic approach targeting data-intensive applications] Reconfigurable hardware has received increasing attention in the past decade due to its adaptable capability and short design time....
Enhancing relocatability of partial bitstreams for runtime reconfiguration (2008)
This paper introduces a method that enhances the relocatability of partial bitstreams for FPGA run-time reconfiguration. Reconfigurable applications usually employ partial bitstreams which are...
This paper introduces a language and framework for designing multiprocessor architectures in the logic programming domain. Our goal is to enable application developers in areas such as machine...
Incremental methods can be used to produce implementations rapidly and to facilitate multi-level design optimisation. This paper describes a declarative framework, based on the language Ruby, that...
C. H. Ho, Wayne Luk, Brad Quinton
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-Chip (SoC). Our...
SELF-OPTIMIZING AND SELF-VERIFYING DESIGN: A VISION (2008)
This paper explores a vision of the design process in which components can optimize and verify themselves to improve efficiency, re-use, and confidence in correctness – the three design challenges...
DOMAIN-SPECIFIC HYBRID FPGA: ARCHITECTURE AND FLOATING POINT APPLICATIONS (2008)
Chun Hok Ho, Chi Wai Yu, Wayne Luk
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient...
Incremental Elaboration for Run-Time Reconfigurable Hardware Designs ABSTRACT (2008)
Arran Derbyshire, Tobias Becker, Wayne Luk
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific...
British Computer Society BCS Deriving Two-Phase Modules for a Multi-Target Hardware Compiler (2008)
Series Professor, C. J. Rijsbergen, J. He, G. Brown, W. Luk, Jifeng He, ...
©Copyright in this paper belongs to the author(s) Published in collaboration with the
Dong-u Lee, John D. Villasenor, Senior Member, Wayne Luk, Senior Member
Abstract — We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a...
Reconfigurable acceleration of robust frequency-domain echo (2008)
Chun Hok Ho, Ka Fai, Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk
cancellation
Hardware Efficient Algorithm for Image Registration of Real-time Video and Image Data (2008)
This paper is concerned with image registration as applied to video sequences that have been subjected to geometric distortions. It describes the development of two computationally efficient...
Dong-u Lee, Altaf Abdul Gaffar, Student Member, Oskar Mencer, Wayne Luk, ...
Abstract — We present MiniBit, an automated static approach for optimizing bit-widths of fixed-point feedforward designs with guaranteed accuracy. Methods to minimize both the integer and fraction...
a Discrete Fourier Transform implementation and (2008)
Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Nabeel Shirazi
Automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value...
Synthia: Synthesis of Interacting Automata targeting LUT-based FPGAs (2008)
George A. Constantinides, Wayne Luk
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach uses a novel FSM...
Aids—automatic synthesis, optimization (2008)
Dong-u Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts...
IEEE TRANSACTIONS ON COMPUTERS 1 Optimizing Hardware Function Evaluation (2008)
Dong-u Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
Abstract — We present a methodology and an automated system for function evaluation unit generation. Our system selects the best function evaluation hardware for a given function, accuracy...
Chi Wai Yu, Julien Lamoureux, Wayne Luk
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
Framework and Tools for Run-Time Recon gurable Designs (2007)
This paper describes a framework and tools for automating the production of designs that can be partially recon gured at run time. The approach involves several stages, including: (i) a partial...
Submitted to FPL’99 SONIC- A Plug-In Architecture for Video Processing (2007)
Simon D. Haynes, Wayne Luk, John Stone
This paper presents the SONIC reconfigurable computing architecture and our implementation, SONIC-1. SONIC is designed to support the software plug-in methodology to accelerate video image processing...
Customising Flexible Instruction Processors: A Tutorial Introduction (2007)
Abstract. This paper presents a tutorial about the Flexible Instruction
Memory Access Optimization for Recongurable Systems (2007)
This paper discusses memory access optimization for FPGA-based recongurable systems with a hierarchy of on-chip and o-chip (external) memory to speed up applications limited by memory access speed....
surface patches. In Eurographics '87, 1987. (2007)
Theoharis Theoharis, David Duce, Distributed Computing, Systems Programme Iee, Jifeng He, Wayne Luk, ...
[48] Ian Page. Hardware and software for parallel update of raster graphics images. In
of Computing, 8(5):607--616, 1996. (2007)
Mark Harman, Dan Simpson, Carroll Morgan, Annabelle Mciver, Karen Seidel, ...
[186] Nancy Lynch and Frits Vaandrager. Action transducers and timed automata.
Gaussian random number generators (2007)
David B. Thomas, Wayne Luk, John D. Villasenor
Rapid generation of high quality Gaussian random numbers is a key capability for simulations across a wide range of disciplines. Advances in computing have brought the power to conduct simulations...
Hybrid FPGAs- Architecture, Tools and Floating Point Applications (2007)
Philip Leong, Chun Hok Ho, Chi Wai Yu, Wayne Luk, Steve Wilton
� Fixed point computation dominant in FPGA designs due to speed and efficiency � Floating point FPGAs suitable for DSP and
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis (2006)
Dong-u Lee, John D. Villasenor, Senior Member, Wayne Luk, Senior Member
Abstract—We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a...
Robert Dimond, Oliver Pell, Oskar Mencer, Wayne Luk
Application Specific Instruction Processors (ASIPs) provide enhanced performance by directly implementing application segments in hardware as custom instructions. Recent work [1, 2] automates...
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection (2005)
Fahmy, Suhaib A., Cheung, Peter Y. K., Luk, Wayne
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent structure of the HMM...
Reconfigurable Elliptic Curve Cryptosystems on a Chip (2005)
Cheung, Ray C. C., Luk, Wayne, Cheung, Peter Y. K.
This paper presents a System-on-a-Chip (SoC) architecture for Elliptic Curve Cryptosystems (ECC) which targets reconfigurable hardware. A four-level partitioning scheme is described for exploring the...
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems (2005)
Rissa, Tero, Donlin, Adam, Luk, Wayne
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform...
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems (2005)
Rissa, Tero, Donlin, Adam, Luk, Wayne
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform...
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection (2005)
Fahmy, Suhaib A., Cheung, Peter Y. K., Luk, Wayne
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent structure of the HMM...
Reconfigurable Elliptic Curve Cryptosystems on a Chip (2005)
Cheung, Ray C. C., Luk, Wayne, Cheung, Peter Y. K.
This paper presents a System-on-a-Chip (SoC) architecture for Elliptic Curve Cryptosystems (ECC) which targets reconfigurable hardware. A four-level partitioning scheme is described for exploring the...
Optimising transformations for hardware compilation (2005)
Ashley Brown, Wayne Luk, Paul Kelly
This poster presents a transformation system for an industrial-strength parallel language targeting reconfigurable hardware implementations. Its effectiveness has been demonstrated by realistic,...
Customizable elliptic curve cryptosystems (2005)
Student Member, Wayne Luk, Senior Member
Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the...
A hardware Gaussian noise generator using the Wallace method (2005)
Dong-u Lee, Wayne Luk, John D. Villasenor, Senior Member, Guanglie Zhang, ...
Abstract—We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density...
CUSTARD - a customisable threaded FPGA soft processor and tools (2005)
Robert G. Dimond, Oskar Mencer, Wayne Luk
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generated custom...
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs (2004)
Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the...
Automated combination of simulation and hardware prototyping (2004)
This paper presents InterSim, a design method that automates the combination of software simulation and hardware prototyping for application development targeting platforms based on reconfigurable...
Customisable hardware compilation (2004)
Tim Todman, José Gabriel, F. Coutinho, Wayne Luk
Hardware compilers for high-level languages are increasingly recognised to be the key to reducing the productivity gap for advanced circuit development in general, and for reconfigurable designs in...
Adaptive range reduction for hardware function evaluation (2004)
Dong-u Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
Function evaluation f(x) typically consists of range reduction and the actual function evaluation on a small interval. In this paper, we investigate optimization of range reduction given the range...
Automating optimized table-with-polynomial function evaluation for FPGAs (2004)
Dong-u Lee, Oskar Mencer, David J. Pearce, Wayne Luk
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation efficiently, the...
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs (2004)
Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the...
The impact of pipelining on energy per operation in field-programmable gate arrays (2004)
Abstract. This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera...
A flexible hardware encoder for Low-Density Parity-Check Codes (2004)
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding complexity than...
Branch optimisation techniques for hardware compilation (2003)
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating more resources to...
A hardware Gaussian noise generator for channel code evaluation (2003)
Dong-u Lee, Wayne Luk, John Villasenor
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardware-based Gaussian...
Towards Verifying Parametrised Hardware Libraries with Relative Placement Information (2003)
Steve McKeever, Wayne Luk, Arran Derbyshire
This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a simple declarative language...
Combining Imperative and Declarative Hardware Descriptions (2003)
This paper describes an approach for hardware development that involves both imperative and declarative descriptions. The imperative descriptions are mainly used for algorithm and application...
Design Space Exploration with A Stream Compiler (2003)
Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk
We consider speeding up general-purpose applications with hardware accelerators. Traditionally hardware accelerators are tediously hand-crafted to achieve top performance. ASC (A Stream Compiler)...
Design space exploration with A Stream Compiler (2003)
Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk
We consider speeding up general-purpose applications with hardware accelerators. Traditionally hardware accelerators are tediously hand-crafted to achieve top performance. ASC (A Stream Compiler)...
Non-uniform segmentation for hardware function evaluation (2003)
Dong-u Lee, Wayne Luk, John Villasenor
Abstract. This paper presents a method for evaluating functions in hardware based on polynomial approximation with non-uniform segments. The novel use of nonuniform segments enables us to approximate...
Wordlength Optimization for Linear Digital Signal Processing (2003)
George A. Constantinides, Wayne Luk
Abstract—This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two...
A hardware Gaussian noise generator for channel code evaluation (2003)
Dong-u Lee, Wayne Luk, John Villasenor
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardware-based Gaussian...
Reconfigurable shapeadaptive template matching architectures (2002)
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video frames. SA-TM is an...
Reconfigurable shapeadaptive template matching architectures (2002)
This paper presents reconfigurable computing strategies for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video frames. A generic systolic...
A digit-serial structure for reconfigurable multipliers (2001)
Chakkapas Visavakul, Wayne Luk
Abstract. This paper presents a design for combining reconfigurable multiplier array known as Flexible Array Blocks (FABs) and digit-serial techniques to implement arbitrary size multipliers with...
Task-parallel Programming of Reconfigurable Systems (2001)
Abstract. This paper presents task-parallel programming, a style of application development for reconfigurable systems. Task-parallel programming enables efficient interaction between concurrent...
Markus Weinhardt, Ieee Computer Society, Wayne Luk
This paper presents pipeline vectorization, a method for synthesizing hardware pipelines based on software vectorizing compilers. The method improves efficiency and ease of development of hardware...
The Multiple Wordlength Paradigm (2001)
George Constantinides Peter, Wayne Luk
This paper presents a paradigm for the design of multiple wordlength parallel processing systems for DSP applications, based on varying the wordlength and scaling of each signal in a DSP block...
Parameterized function evaluation for FPGAs (2001)
Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between (1) full-lookup...
Evaluating Hardware Compilation Techniques (2000)
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for recongurable computing systems...
Customising Graphics Applications: Techniques and Programming Interface (2000)
Henry Styles And, Henry Styles, Wayne Luk
This paper identifies opportunities for customising architectures for graphics applications, such as infrared simulation and geometric visualisation. We have studied methods for exploiting custom...
Plug-in Processing Elements (p. 52) (2000)
Simon D. Haynes, John Stone, Wayne Luk
• Partitions between Hardware & Software – Tend to be automatic or manual based on frequency requirements – How often is the need to reconfigure: • Multiple times per frame? • Different...
Towards Portable Hierarchical Placement for FPGAs (1999)
Dupont De Dinechin, Florent, Luk, Wayne, Mckeever, Steve
Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to the new...
Towards Portable Hierarchical Placement for FPGAs. (1999)
De Dinechin, Florent, Luk, Wayne, McKeever, Steve
(eng) Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to...
Towards Portable Hierarchical Placement for FPGAs (1999)
De Dinechin, Florent, Luk, Wayne, Mckeever, Steve
Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to the new...
Towards Portable Hierarchical Placement for FPGAs (1999)
De Dinechin, Florent, Luk, Wayne, Mckeever, Steve
Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to the new...
SONIC -- a Plug-In Architecture for Video Processing (1999)
Simon D. Haynes, Wayne Luk, John Stone
This paper presents the SONIC reconfigurable computing architecture and the first implementation, SONIC-1. SONIC is designed to support the software plug-in methodology to accelerate video image...
Pipeline Vectorization for Recon gurable Systems (1999)
Markus Weinhardt And, Markus Weinhardt, Wayne Luk
This paper presents pipeline vectorization, a method for synthesizing hardware pipelines in recongurable systems based on software vectorizing compilers. The method improves eciency and ease of...
Towards Portable Hierarchical Placement for FPGAs (1999)
Ecole Normale, Superieure Lyon, Unite Mixte, Florent De Dinechin, Wayne Luk, ...
Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to the new...
Pipeline Vectorization for Reconfigurable Systems (1999)
This paper presents pipeline vectorization, a method for synthesizing hardware pipelines in reconfigurable systems based on software vectorizing compilers. The method improves efficiency and ease of...
Automating Production of Run-Time Reconfigurable Designs (1998)
This paper describes a method that automates a key step in producing run-time recon gurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit...
Synthesis and Implementation of Pipeline Circuits on Partially Reconfigurable FPGAs (1998)
1 Introduction This paper presents a pipeline synthesis framework for partially reconfigurable FPGAs. Our aim is to automatically exploit partial reconfiguration. The research is based on our...
Pebble: a language for parametrised and reconfigurable hardware design (1998)
Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be...
A Reconfigurable Engine for Real-Time Video Processing (1998)
Wayne Luk, W. Luk, Arran Derbyshire, P. Andreou, A. Derbyshire, Nabeel Shirazi, ...
. We describe the hardware and software extensions that transform a PC-based low-cost FPGA system into a reconfigurable engine for real-time video processing. The hardware extensions include a...
Pebble: A Language for Parametrised and Reconfigurable Hardware Design (1998)
Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which canbe...
Pebble: A Language For Parametrised and Reconfigurable Hardware Design (1998)
Abstract. Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions...
Compilation tools for run-time recon gurable designs (1997)
Wayne Luk, Nabeel Shirazi, Sw Bz
This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con...
Compilation tools for run-time reconfigurable designs (1997)
This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: (i) a partial evaluator, which produces...
Visualising Reconfigurable Libraries for FPGAs (1997)
This paper describes a framework and tools for visualising hardware libraries for Fleld-Programmable Gate Arrays (FPGAs), which should also be useful for circuit design in general. Our approach...
Riley-2: A Flexible Platform for Codesign and Dynamic Reconfigurable Computing Research (1997)
Patrick Mackinlay Peter, Wayne Luk, Richard S
: The paper first proposes requirements for an ideal platform for codesign research. A new board developed at Imperial College, the Riley-2, is shown to meet these requirements. It is a PCI based...
Compilation Tools for Run-Time Reconfigurable Designs (1997)
This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: (i) a partial evaluator, which produces...
Abstract. We have previously developed a verified algorithm for compiling programs written in an occam-like language into delay-insensitive circuits. In this paper we show how to retarget our...
Modelling and Optimising Run-Time Reconfigurable Systems (1996)
Wayne Luk, Nabeel Shirazi, Sw Bz
We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented...
Modelling and Optimising Run-Time Reconfigurable Systems (1996)
Wayne Luk, Nabeel Shirazi, Sw Bz
We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented...
Modelling and Optimising Run-Time Reconfigurable Systems (1996)
We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented...
Modelling and Optimising Run-Time Reconfigurable Systems (1996)
Wayne Luk, Nabeel Shirazi, Sw Bz
We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented...
Compiling Ruby into FPGAs (1995)
. This paper presents an overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs. The features of two important modules, the refinement module and...
Hardware-Software Codesign of Multidimensional Programs (1994)
We present a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-andconquer structure, with the...
Structured Hardware Compilation of Parallel Programs (1994)
Wayne Luk, David Ferguson, Ian Page
A major bottleneck in automatic hardware synthesis is the time to place and route the netlist produced by a hardware compiler. This paper presents a method which exploits the syntax of the source...
Towards a Declarative Framework for Hardware-Software Codesign (1994)
We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for parametrised...
Constraint-based Hierarchical Placement of Parallel Programs (1994)
. This paper continues our investigation into the feasibility of exploiting the structure of a parallel program to guide its hardware implementation. We review previous work, and present our new...
Using Reconfigurable Hardware to Speed up Product Development and Performance (1994)
Adrian Lawrence, Andrew Kay, Wayne Luk, Toshio Nomura, Ian Page
. Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array...
Compilation of Programs into Hardware and Software (1994)
this document which have been, and continue to be, a genuinely inter-disciplinary collaborative venture. In addition, Tony Hoare and Bob McLatchie have been strongly supportive of this work in every...
Structured hardware compilation of parallel programs (1994)
A major bottleneck in automatic hardware synthesis is the time to place and route the netlist produced by a hardware compiler. This paper presents a method which exploits the syntax of the source...
Towards a declarative framework for hardware-software codesign (1994)
We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for parametrised...
Hardware Acceleration of Divide-and-Conquer Paradigms: a Case Study (1993)
Wayne Luk, Vincent Lok, Ian Page
We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the "divide" and...
Optimising Designs By Transposition (1991)
this paper is fourfold: first, to describe some observations about how arraybased designs can be optimised by transposition -- a method of rearranging components and their interconnections; second,...
Compiling Occam into Field-Programmable Gate Arrays (1991)
We describe a compiler which maps programs expressed in a subset of occam into netlist descriptions of parallel hardware. Using Field-Programmable Gate Arrays to implement such netlists,...
Compiling Occam into Field-Programmable Gate Arrays (1991)
We describe a compiler which maps programs expressed in a subset of occam into netlist descriptions of parallel hardware. Using Field-Programmable Gate Arrays to implement such netlists,...
Compiling Occam into Field-Programmable Gate Arrays (1991)
We describe a compiler which maps programs expressed in a subset of occam into netlist descriptions of parallel hardware. Using Field-Programmable Gate Arrays to implement such netlists,...
Analysing Parametrised Designs By Non-Standard Interpretation (1990)
. We examine the use of non-standard interpretation to analyse parametrised circuit descriptions, in particular for array-based architectures. Various metrics are employed to characterise the...
A systolic LRU processor and its top-down development (1990)
. We present a novel systolic processor that implements the leastrecently -used (LRU) policy for multi-level storage systems. The design is developed by successively refining a high-level description...
Computer-Based Tools For Regular Array Design (1989)
Wayne Luk, Geraint Jones, Mary Sheeran
. We present an overview of a prototype system based on a functional language for developing regular array circuits. The features of a simulator, floorplanner and expression transformer are discussed...
A Comment on the Implementation of the Ziggurat Method
Ganglie Zhang, Dong-U Lee, Wayne Luk, John Villasenor
We show that the short period of the uniform random number generator in the published implementation of Marsaglia and Tsang’s Ziggurat method for generating random deviates can lead to poor...
Compiling Occam into Field-Programmable Gate Arrays
We describe a compiler which maps programs expressed in a subset of occam into netlist descriptions of parallel hardware. Using Field-Programmable Gate Arrays to implement such netlists,...
Automating Production of Run-Time Reconfigurable Designs
This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit...
Retargeting a Hardware Compiler Proof using Protocol Converters
Geoffrey Brown, Wayne Luk, John O'Leary
We show how to retarget the correctness proof of a hardware compiler generating two-phase delayinsensitive circuits to a compiler generating four-phase speed-independent circuits. We use protocol...