N. Kranitis 1 Low-Cost Software-Based Self-Testing of RISC Processor Cores (2008)
G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian
Software self-testing of embedded processor cores which effectively partitions the testing effort between lowspeed external equipment and internal processor resources, has been recently proposed as...
Fault-Secure Shifter Design: Results and Implementations (2007)
Ricardo O. Duarte, M. Nicolaidis, H. Bederr, Y. Zorian
Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This...
Relay Propagation Scheme for Testing of MCMs on Large Area Substrates Abstract (2007)
K. Sasidhar, A. Chatterjee, Y. Zorian
This paper addresses the issue of testing MCMs on large area substrates. The cost of testing MCMs may be as high as 40 % of the total manufacturing cost. It is critical that the test process be...
com/archive/articles/0103ate.htm (2003)
S. Dey, E. J. Marinissen, Y. Zorian, Test Access Methodology, F. M. Bufler, Y. Asahi, ...
VIII. CONCLUSION In this paper, an efficient implementation of a TAM is proposed for the MSOC testing. The technique introduces I/O access of the analog cores through the MTAM switch, which is...
Application and Analysis of RT-Level SoftwareBased Self-testing for Embedded Processor Cores (2003)
N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian
Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based...
Effective software self-test methodology for processor cores (2002)
N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing...
Scaling deeper to submicron: on-line testing to the rescue (1999)
Summary form only given. Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities....
On-line testing for VLSI-a compendium of approaches (1998)
This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance; self-checking design, allowing high quality concurrent checking...
Efficient totally self-checking shifter design (1998)
Nicolaidis, M., Bederr, H., Zorian, Y.
Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This...
RAM-Based FPGA's: A Test Approach for the Configurable Logic (1998)
M. Renovell, J. M. Portal, J. Figueras, Y. Zorian
Abstract: This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated...
Fault-secure shifter design: results and implementations (1997)
Nicolaidis, M., Bederr, H., Zorian, Y.
Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This...
Area versus detection latency trade-offs in self-checking memory design (1995)
Kebichi, O., Zorian, Y., Nicolaidis, M.
With the increasing need for on-line reliability today's electronic systems often require certain levels of self-checking. Depending on its application, the level of self-checking, i.e. the detection...
An approach for designing total-dose tolerant MCMs based on current monitoring (1995)
Vargas, F., Nicolaidis, M., Zorian, Y.
This paper presents a new technique for designing reliable multichip modules (MCMs) under radiation effects for spacecraft electronics. The technique is based on current monitoring to detect faults...
Krishnendu Chakrabarty, John R Hayes, Y. Zorian
Abstract. We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome...