Abstract Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture £ (2009)
Seongbeom Kim, Dhruba Ch, Yan Solihin
This paper presents a detailed study of fairness in cache sharing between threads in a chip multiprocessor (CMP) architecture. Prior work in CMP architectures has only studied throughput optimization...
Seongbeom Kim, Fang Liu, Yan Solihin, Ravi Iyer, Li Zhao, William Cohen
The ongoing trend of increasing computer hardware and software complexity has resulted in the increase in complexity and overheads of cycle-accurate processor system simulation, especially in...
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (2008)
Dhruba Ch, Fei Guo, Seongbeom Kim, Yan Solihin
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-uniformly, where some...
Abstract Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture (2008)
Seongbeom Kim, Dhruba Ch, Yan Solihin
This paper presents a detailed study of fairness in cache sharing between threads in a chip multiprocessor (CMP) architecture. Prior work in CMP architectures has only studied throughput optimization...
Abstract Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (2008)
Dhruba Ch, Fei Guo, Seongbeom Kim, Yan Solihin
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads nonuniformly, where some...
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture £ (2008)
Dhruba Ch, Fei Guo, Seongbeom Kim, Yan Solihin
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-uniformly, where some...
Reservation Station Architecture for Mutable Functional Unit Usage in Superscalar Processors (2008)
Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
One major bottleneck of a superscalar processor is mismatch of instruction stream mix with functional unit configuration. Depending on the type and number of functional units, the performance loss...
Grey-Scale Image Thresholding for Specific Applications (2008)
Yan Solihin, C. G. Leedham, Yan Solihin, C. G. Leedham, Yan Solihin, C. G. Leedham
Summary. A thresholding approach that performs thresholding stage by stage on grey scale images is discussed. The ability to exploit various information from the image to assist the assignment of a...
Mazen Kharbutli, Xiaowei Jiang, Yan Solihin, Heap Server
The goal of this paper is to propose a scheme that provides comprehensive security protection for the heap. Heap vulnerabilities are increasingly being exploited for attacks on computer programs. In...
Rithin Shetty, Mazen Kharbutli, Yan Solihin, Milos Prvulovic
Detection of memory-related bugs is a very important aspect of the software development cycle, yet there are not many reliable and efficient tools available for this purpose. Most of the tools and...
Brian Rogers, Siddhartha Chhabra, Yan Solihin
In today’s digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors which utilize hardware-based memory...
Flexitaint: A programmable accelerator for dynamic taint propagation (2008)
Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic
This paper presents FlexiTaint, a hardware accelerator for dynamic taint propagation. FlexiTaint is implemented as an in-order addition to the back-end of the processor pipeline, and the taints for...
Memory Hierarchy Model Validation (2007)
Yan Solihin, Yong Luo, Kirk Cameron
The memory hierarchy model is a powerful tool that can separate the stall time in a multi-level cache. However, since no tool currently exists that is able to compute this information, it is...
Dynamically Mutable Functional Unit in Superscalar Processors (2007)
Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
One major bottleneck of a superscalar processor is the mismatch of instruction stream mix with functional unit configuration. Depending on the type and number of functional units, the performance...
Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier
2 Florida Institute of Technology,
1 Reservation Station Architecture for Mutable Functional Unit Usage in (2007)
Superscalar Processors, Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
One major bottleneck of a superscalar processor is mismatch of instruction stream mix with functional unit configuration. Depending on the type and number of functional units, the performance loss...
A Framework for Providing Quality of Service in Chip Multi-Processors (2007)
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse in terms of...
QoS Policy and Architecture for Cache/Memory in CMP Platforms (2007)
Ravi Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Don Newell, ...
As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the simultaneous workloads running on them is expected to increase. The rapid deployment of...
PERFORMANCE COMPARISON OF SOFTWARE TRANSACTIONAL MEMORY IMPLEMENTATIONS (2007)
Software Transactional Memory (STM), an optimistic concurrency control mechanism for controlling accesses to shared memory, is a promising alternative to lock-based mutual exclusion strategies. A...
Improving Cost, Performance, and Security of Memory Encryption and Authentication (2006)
Chenyu Yan, Brian Rogers, Daniel Englender, Yan Solihin, Milos Prvulovic
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication...
Improving Cost, Performance, and Security of Memory Encryption and Authentication (2006)
Chenyu Yan, Brian Rogers, Daniel Englender, Yan Solihin, Milos Prvulovic
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication...
Comprehensively and efficiently protecting the heap (2006)
Mazen Kharbutli, Xiaowei Jiang, Yan Solihin
The goal of this paper is to propose a scheme that provides comprehensive security protection for the heap. Heap vulnerabilities are increasingly being exploited for attacks on computer programs. In...
Efficient Data Protection for Distributed Shared Memory Multiprocessors (2006)
Brian Rogers, Milos Prvulovic, Yan Solihin
Data security in computer systems has recently become an increasing concern, and hardware-based attacks have emerged. As a result, researchers have investigated hardware encryption and authentication...
Helper Thread Prefetching for Loosely-Coupled Multiprocessor Systems (2006)
Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an intelligent memory...
Improving Cost, Performance, and Security of Memory Encryption and Authentication (2006)
Chenyu Yan, Brian Rogers, Daniel Englender, Yan Solihin, Milos Prvulovic
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication...
Improving Cost, Performance, and Security of Memory Encryption and Authentication (2006)
Chenyu Yan, Brian Rogers, Daniel Englender, Yan Solihin, Milos Prvulovic
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication...
Counter-based cache replacement algorithms (2005)
Recent studies have shown that in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large, suggesting that...
Fair cache sharing and partitioning in a chip multiprocessor architecture (2004)
Seongbeom Kim, Dhruba Ch, Yan Solihin
This paper presents a detailed study of fairness in cache sharing between threads in a chip multiprocessor (CMP) architecture. Prior work in CMP architectures has only studied throughput optimization...
Using prime numbers for cache indexing to eliminate conflict misses (2004)
Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin Lee
Using alternative cache indexing/hashing functions is a popular technique to reduce conflict misses by achieving a more uniform cache access distribution across the sets in the cache. Although...
Memory Predecryption: Hiding the Latency Overhead of Memory Encryption (2004)
Brian Rogers, Yan Solihin, Milos Prvulovic
Memory encryption has become a common approach to providing a secure processing environment, but current schemes suffer from extra performance and storage overheads. This paper presents predecryption...
Correlation Prefetching with a User-Level Memory Thread (2003)
Yan Solihin, Jaejin Lee, Josep Torrellas, Senior Member
This paper proposes using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory...
Using a user-level memory thread for correlation prefetching (2002)
Yan Solihin, Jaejin Lee, Josep Torrellas
Abstract This paper introduces the idea of using a User-Level Memory Thread(ULMT) for correlation prefetching. In this approach, a user thread
The Multi-stage Approach to Grey-Scale Image Thresholding for Specific Applications (2002)
Yan Solihin, Yan Solihin, C. G. Leedham, C. G. Leedham
Summary. A thresholding approach that performs thresholding stage by stage on grey scale images is discussed. The ability to exploit various information from the image to assist the assignment of a...
Using a User-Level Memory Thread for Correlation Prefetching (2002)
Yan Solihin Jaejin, Yan Solihin, Jaejin Lee, Josep Torrellas
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in...
Using a User-Level Memory Thread for Correlation Prefetching (2002)
Yan Solihin Jaejin, Yan Solihin
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in...
Automatic Code Mapping on an Intelligent Memory Architecture (2001)
Yan Solihin, Jaejin Lee, Josep Torrellas
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a high-end host processor and a simpler memory processor. To achieve high...
Automatically mapping code on an intelligent memory architecture (2001)
Jaejin Lee, Yan Solihin, Josep Torrellas
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high performance with...
Automatically mapping code on an intelligent memory architecture (2001)
Jaejin Lee, Yan Solihin, Josep Torrellas
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high performance with...
Automatic Code Mapping on an Intelligent Memory Architecture (2001)
Yan Solihin, Student Member, Jaejin Lee, Josep Torrellas, Senior Member
AbstractÐThis paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a highend host processor and a simpler memory processor.To achieve high...
Adaptatively Mapping Code in an Intelligent Memory Architecture (2000)
Yan Solihin, Jaejin Lee, Josep Torrellas
Abstract. This paper presents an algorithm to automatically map code to a generic Processor-In-Memory (PIM) system that consists of a host processor and a much simpler memory processor. To achieve...
An application scalability model for distributed shared memory machines /--by Yan Solihin. (1999)
Vita.
Scal-tool: Pinpointing and quantifying scalability bottlenecks in dsm multiprocessors (1999)
Yan Solihin, Vinh Lam, Josep Torrellas
Abstract Distributed Shared-Memory (DSM) multiprocessors provide an attractive combination of cost-effective commodity architecture and, thanks to the shared-memory abstraction, relative ease of...
Exploiting Application Parallelism Using Advanced Intelligent Memory - The FlexRAM Approach (1999)
Wei Huang, B. Eng, Sujoy Basu, Qiang Cao, Marcelo Cintra, Zhenzhou Ge, ...
The state-of-the-art microprocessor employs tens of millions of transistors on a single chip, most of them are used to tackle the problem of slow memory. While these processors demonstrate great...
Scal-tool: Pinpointing and quantifying scalability bottlenecks in dsm multiprocessors (1999)
Yan Solihin, Vinh Lam, Josep Torrellas
Distributed Shared-Memory (DSM) multiprocessors provide an attractive combination of cost-effective commodity architecture and, thanks to the shared-memory abstraction, relative ease of programming....
Boosting the Speedup of Future Processor Architectures by Using Mutable Functional Units (1999)
Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
One major bottleneck of a superscalar processor is the mismatch of instruction stream mix with functional unit configuration. The resulting "unavailable functional unit" stalls can be a...
Integer/Floating-point Reconfigurable ALU (1999)
Dominique Lavenier, Yan Solihin, Kirk Cameron
This report describes a functional unit able to perform both usual integer operations and oating-point additions. Basically, the architecture extends the structure of a floating-point adder, so that...
Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors (1999)
Yan Solihin, Vinh Lam, Josep Torrellas
Distributed Shared-Memory (DSM) multiprocessors provide an attractive combination of cost-eective commodity architecture and, thanks to the shared-memory abstraction, relative ease of programming....