Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid (2008)
Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
Abstract—In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer’s routing grid space, coupling effects...
A Low-Power Digital Matched Filter for Spread-Spectrum Systems (2008)
Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada
A Digital Matched Filter (DMF) is an essential device for Direct-Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for...
Routing Methodology for Minimizing Interconnect Energy Dissipation (2008)
Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita
In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology,...
Yoshifumi Matsushita, Yasoo Harada
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS)...
Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid (2003)
Sakai, Atsushi, Yamada, Takashi, Matsushita, Yoshifumi, Yasuura, Hiroto, 坂井, 篤, 山田, 節, ...
In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer’s routing grid space, coupling effects such as...
Routing Methodology for Minimizing lnterconnect Energy Dissipation (2003)
Sakai, Atsushi, Yamada, Takashi, Matsushita, Yoshifumi, Yasuura, Hiroto, 坂井, 篤, 山田, 節, ...
In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology,...
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid (2003)
Sakai, Atsushi, Yamada, Takashi, Matsushita, Yoshifumi, Yasuura, Hiroto, 坂井, 篤, 山田, 孝, ...
In this paper, we propose novel physical design techniques for a sub-quarter micron system-on-a-chip (SoC). By appropriately optimizing the routing grid space or the cell utilization ratio, the...
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA (2002)
Goto, Shoji, Yamada, Takashi, Takayama, Norihisa, Matsushita, Yoshifumi, Harada, Yasoo, Yasuura, Hiroto, ...
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS)...
Power Analysis Techniques for SoC with Improved Wiring Models (2002)
Sakamoto, Takeshi, Yamada, Takashi, Mukuno, Mamoru, Matsushita, Yoshifumi, Harada, Yasoo, Yasuura, Hiroto, ...
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout...
A Low-Power Digital Matched Filter for Spread-Spectrum Systems (2002)
Goto, Shoji, Yamada, Takashi, Takayama, Norihisa, Matsushita, Yoshifumi, Harada, Yasoo, Yasuura, Hiroto, ...
A Digital Matched Filter (DMF) is an essential device for Direct- Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for...