Kohara, Shunitsu, Tomono, Naoki, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
A Processor Core Synthesis System in IP-based SoC Design (2005)
Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
A Processor Core Synthesis System in IP-based SoC Design (2005)
Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis (2005)
KAWAZU, Hideki, UCHIDA, Jumpei, MIYAOKA, Yuichiro, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo
A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k × n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor...
TOGAWA, Nozomu, TACHIKAKE, Koichi, MIYAOKA, Yuichiro, YANAGISAWA, Masao, OHTSUKI, Tatsuo
This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm...
A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths (2004)
Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
Instruction Set and Functional Unit Synthesis for SIMD Processor Cores (2004)
Togawa, Nozomu, Tachikake, Koichi, Miyaoka, Yuichiro, Yanagisawa, Masao, Ohtsuki, Tatsuo
A hardware/software partitioning algorithm for SIMD processor cores (2003)
Tachikake, Koichi, Miyaoka, Yuichiro, Choi, Jinku, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo
A hardware/software partitioning algorithm for SIMD processor cores (2003)
Tachikake, Koichi, Miyaoka, Yuichiro, Choi, Jinku, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo