3 Now at Lattice Semiconductor Contents (2008)
Adnan Aziz, Robert Brayton, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Abelardo Pardo, ...
Abstract A Redesign Technique for Combinational Circuits Based on Gate Reconnections (2008)
Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
In this paper, we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting...
Combinational Verification Based on High-Level Functional Specifications (2008)
Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
We present a new combinational verification technique where the functional specification of a circuit under verification is utilized to simplify the verification task. The main idea is to assign to...
Speeding up SAT Based ATPG for Logic Verification by Recursive Learning (2007)
Min Zhou, Yuji Kukimoto, Huey-yih Wang
Recursive Learning (RL) is a circuit-structure-based method for computing all necessary assignments. Recursive learning technique can be combined with different CAD algorithms and techniques in...
Improving the Reachability Analysis Technique by Circuit (2007)
Implicit reachable state computation can be applied to a wide range of sequential formal verification and logic synthesis problems. Symbolic manipulation with BDDs is one of the most efficient...
Refining switching window by time slots for crosstalk noise calculation (2002)
Pinhong Chen, Yuji Kukimoto, Kurt Keutzer
For crosstalk noise calculation, computing switching windows of a net helps us identify noise sources accurately. Traditional approaches use a single continuous switching window for a net. Under this...
Timing analysis and optimization for high-performance digital circuits /--by Yuji Kukimoto. (1998)
Thesis (Ph. D. in Engineering-Electrical Engineering and Computer Sciences)--University of California, Berkeley, Fall 1998.
Hierarchical Functional Timing Analysis (1998)
Yuji Kukimoto, Robert K. Brayton
We propose a hierarchical timing analysis technique for combinational circuits under the tightest known sensitization criterion, the XBD0 delay model. Given a hierarchical combinational circuit, a...
Delay-optimal technology mapping by DAG covering (1998)
Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped...
Delay Characterization of Combinational Modules (1998)
Yuji Kukimoto, Robert K. Brayton
We address three related issues on timing characterization of combinational modules. We first introduce a new notion called timing safe-replaceability as a way of comparing the timing characteristics...
Delay-Optimal Technology Mapping by DAG Covering (1998)
Yuji Kukimoto, Robert K. Brayton, Prashant Sawkary
We propose an optimal algorithm for delay minimal technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be...
Delay Characterization of Combinational Modules by Functional Arrival Time Analysis (1998)
Yuji Kukimoto, Robert K. Brayton
A combinational module is a combinational circuit that can be used under any arrival time condition. In [8] we showed that exact false-path-aware delay characterization of a combinational module can...
Delay-Optimal Technology Mapping by DAG Covering (1998)
Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped...
Delay-optimal technology mapping by DAG covering (1998)
Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped...
Hierarchical Functional Timing Analysis (1998)
Yuji Kukimoto, Robert K. Brayton
We propose a hierarchical timing analysis technique for combinational circuits under the tightest known sensitization criterion, the XBD0 delay model. Given a hierarchical combinational circuit, a...
Exact required time analysis via false path detection (1997)
Yuji Kukimoto, Robert K. Brayton
This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on...
Canonical TBDD's and Their Application to Combinational Verification (1997)
Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
We propose a new class of decision diagrams called canonical cube transformation binary decision diagrams (canonical TBDD's), which is an extension of TBDD's proposed by Meinel et al [11,...
Exact Required Time Analysis via False Path Detection (1997)
Yuji Kukimoto, Robert K. Brayton
This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on...
Computing Delay with Coupling Using Timed Automata (1997)
Serdar Tasiran, Yuji Kukimoto, Robert K. Brayton
ion corresponds to overapproximating F . (ii) Image computation is performed by "propagating wavefronts" across the partitions. This corresponds to performing the composition of the...
Computing Delay with Coupling using Timed Automata (1997)
Yuji Kukimoto, Robert K. Brayton
Deep sub-micron circuits place new requirements on timing analysis tools: More accuracy is needed and new effects such as pattern dependent delays and cross-talk must be modeled. We propose a...
VIS: A System for Verification and Synthesis (1996)
Alberto Sangiovanni-Vincentelli, Adnan Aziz, Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, ...
ion Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all the...
BDD Minimization by Truth Table Permutations (1995)
Masahiro Fujita Yuji, Yuji Kukimoto, Robert K. Brayton
Bern, Meinel and Slobodova [1] have recently proposed a novel technique called cube transformations to minimize the size of binary decision diagrams. Given a Boolean function, they try to find a...
BDD Minimization by Truth Table Permutations (1995)
Masahiro Fujita Yuji, Yuji Kukimoto, Robert K. Brayton
Bern, Meinel and Slobodova [1] have recently proposed a novel technique called cube transformations to minimize the size of binary decision diagrams. Given a Boolean function, they try to find a...
Rectification Method for Lookup-Table Type FPGA's (1992)
Yuji Kukimoto, Masahiro Fujita
Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method...
Application of Boolean Unification to Combinational Logic Synthesis (1991)
Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-chien Chen
Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since the general solution provides a way to represent complete don't care sets in a functional...