Zili Shao, Qingfeng Zhuge, Bin Xiao
In embedded systems, high performance DSP needs to be performed not only with high data throughout but also with low power consumption. It becomes an important problem to reduce the power consumption...
Graph Partitioning Problem Applied to Adaptive Mobile Wireless Networks ∗ (2009)
Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao
In a large-scale adaptive mobile wireless network, long-distance message transfer can be routed by introduced mobile servers while nearby mobile units can contact each other through direct...
Efficient Scheduling for Low-Power High-Performance DSP Applications (2009)
Zili Shao, Qingfeng Zhuge, Youtao Zhang
To process high performance DSP applications in embedded systems, VLIW (Very Long Instruction Word) architecture is widely adopted in high-end DSP processors. While better performance is achieved,...
Zili Shao, Qingfeng Zhuge, Meilin Liu, Chun Xue, Bin Xiao
Algorithms and analysis of scheduling for loops with minimum switching
Zili Shao, Qingfeng Zhuge, Meilin Liu, Chun Xue, Bin Xiao
Algorithms and analysis of scheduling for loops with minimum switching
Qingfeng Zhuge, Bin Xiao, Zili Shao
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application significantly. For most...
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time (2009)
Multiproceesor Dsp, Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao
Dynamic Voltage Scaling (DVS) is one of the techniques used to obtain energy-saving in real-time DSP systems. In many DSP systems, some tasks contain conditional instructions that have different...
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture (2008)
Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new loop scheduling...
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs ⋆ (2008)
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu
Abstract. Loop distribution and loop fusion are two effective loop transformation techniques to optimize the execution of the programs in DSP applications. In this paper, we propose a new technique...
In this paper, we develop a novel real-time instructionlevel loop scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. We first prove that the...
Reducing memory accesses is particularly important for DSP applications since they are widely used in embedded systems and need to be executed with high performance and low power consumption. In this...
Efficient Graph Transformation to Legalize Loop Fusion for VLIW Architectures £ (2008)
Meilin Liu, Qingfeng Zhuge, Zili Shao
Loop fusion is widely used to exploit the instruction-level parallelism by transforming separate loops into one loop for applications of embedded systems. Loop fusion, however, is not always...
ANALYSIS AND ALGORITHMS FOR SCHEDULING WITH MINIMAL SWITCHING ACTIVITIES (2008)
Switching activities are one of the important factors in power minimization. This paper studies the scheduling problem which minimizes switching activities. We show that to find the schedule which...
Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size £ (2008)
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu
In this paper, we propose a technique combining loop distribution with loop fusion to improve the timing performance without increasing the code size of the transformed loops. We first develop the...
Meikang Qiu, Chun Xue, Zili Shao
Energy-saving is extremely important in real-time embedded systems. Dynamic Voltage Scaling (DVS) is one of the prime techniques used to achieve energy-saving. Due to the uncertainties in execution...
Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP £ (2008)
Zili Shao, Chun Xue, Qingfeng Zhuge, Bin Xiao
In embedded systems, high performance DSP needs to be performed not only with high data throughput but also with low power consumption. This paper develops an instruction-level loop scheduling...
Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network ⋆ (2008)
Meikang Qiu, Zili Shao, Qingfeng Zhuge, Meilin Liu
Abstract. Energy and delay are critical issues for wireless sensor networks since most sensors are equipped with non-rechargeable batteries that have limited lifetime. Due to the uncertainties in...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such as software...
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts £ (2008)
Miao Liu, Zili Shao, Meng Wang, Hongxing Wei, Tianmiao Wang
In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. To separate real-time and non-real-time hardware interrupts by hardware, we show that it is...
LOOP SCHEDULING FOR MINIMIZING SCHEDULE LENGTH AND SWITCHING ACTIVITIES (2008)
Switching activity is one of the most important factors in power dissipation. This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications...
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time (2008)
Multiproceesor Dsp, Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao
Dynamic Voltage Scaling (DVS) is one of the techniques used to obtain energy-saving in real-time DSP systems. In many DSP systems, some tasks contain conditional instructions that have different...
Optimizing Address Assignment and Scheduling for DSPs with Multiple Functional Units (2008)
Chun Xue, Zili Shao, Qingfeng Zhuge, Bin Xiao, Meilin Liu
Abstract — DSP processors provide dedicated address generation units (AGUs) that are capable of performing address arithmetic in parallel to the main data path. Address assignment, optimization of...
Optimizing Nested Loops with Iterational and Instructional Retiming ⋆ (2008)
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu
Abstract. Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by increasing the...
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture (2008)
Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new loop scheduling...
Algorithms and Analysis of Scheduling for Low-Power High-Performance DSP on VLIW Processors (2008)
Zili Shao, Qingfeng Zhuge, Youtao Zhang
Abstract — Switching activity and schedule length are the two most important factors that influence the energy consumption of an application executed on a VLIW (Very Long Instruction Word)...
Algorithms and Analysis of Scheduling for Loops with Minimum Switching (2008)
Zili Shao, Qingfeng Zhuge, Meilin Liu, Chun Xue, Bin Xiao
Abstract — Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimizes both schedule length and...
High-level Synthesis for DSP Applications using Heterogeneous Functional Units £ (2008)
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao
Abstract — This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture...
High-level Synthesis for DSP Applications using Heterogeneous Functional Units (2008)
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao
Abstract — This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture...
Design and Analysis of Improved Shortest Path Tree Update for Network Routing ∗ (2008)
Bin Xiao, Qingfeng Zhuge, Zili Shao
The quick construction of the Shortest Path Tree (SPT) is essential to achieve fast routing speed for an interior network using link state protocols, such as OSPF and IS-IS. Whenever the network...
Theory and Algorithms for Software Pipelining with Minimal Cost on Nested Loops (2008)
Software pipelining is one of the most important optimization techniques to increase the parallelism among successive loop iterations. However, little research has been done for the software...
Maximize Parallelism for Nested Loops via Loop Striping (2006)
Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Meikang Qiu
applications are recursive or iterative. Transformation techniques are generally applied to increase parallelism for these nested loops. Most of the existing loop transformations techniques either...
High performance, low power and secure embedded systems (2005)
Embedded systems are driving an information revolution with their pervasion in our everyday lives. The increasingly ubiquitous embedded systems pose a host of technical challenges different from...
and code size via retiming and unfolding * (2005)
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu
Design optimization and space minimization considering timing
Efficient assignment and scheduling for heterogeneous dsp systems (2005)
This paper addresses high level synthesis for real-time digital signal processing (DSP) architec-tures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an...
Minimizing energy via loop scheduling and dvs for multi-core embedded systems (2005)
Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao
Low energy consumptions are extremely important in real-time embedded systems, and scheduling is one of the techniques used to obtain lower energy consumptions. In this paper, we propose loop...
Iterational retiming: Maximize iteration-level parallelism for nested loops (2005)
Chun Xue, Zili Shao, Meilin Liu
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation techniques to increase...
Zili Shao, Chun Xue, Qingfeng Zhuge
Buffer overflow attacks cause serious security problems. Array & pointer bound checking is one of the most effective approaches for defending against buffer overflow attacks when source code is...
Efficient assignment and scheduling for heterogeneous dsp systems (2005)
Zili Shao, Qingfeng Zhuge, Xue Chun
This paper addresses high level synthesis for real-time digital signal processing (DSP) architec-tures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an...
Zili Shao, Chun Xue, Qingfeng Zhuge, Sha Bin, Xiao Ýþ
With more embedded systems networked, it becomes an important problem to effectively defend embedded systems against buffer overflow attacks. Due to the increasing complexity and strict requirements,...
Zili Shao, Chun Xue, Qingfeng Zhuge
With more embedded systems networked, it becomes an important research problem to effectively defend embedded systems against buffer overflow attacks and efficiently check if systems have been...
Zili Shao, Chun Xue, Student Member, Qingfeng Zhuge, Student Member, Bin Xiao, ...
Abstract — With more embedded systems networked, it becomes an important problem to effectively defend embedded systems against buffer overflow attacks. This paper proposes the HSDefender...
Zili Shao, Chun Xue, Student Member, Qingfeng Zhuge, Student Member, Meikang Qiu, ...
more embedded systems networked, it becomes an important problem to effectively defend embedded systems against buffer overflow attacks. Due to the increasing complexity and strict requirements,...
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units (2004)
Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu
In high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs), an important problem is how to assign a proper FU type to each...
Defending embedded systems against buffer overflow via hardware/software (2003)
Zili Shao, Qingfeng Zhuge, Yi He
Buffer overflow attacks have been causing serious security problems for decades. With more embedded systems networked, it becomes an important research problem to defend embedded systems against...
Design space minimization with timing and code size optimization for embedded DSP (2003)
Qingfeng Zhuge, Zili Shao, Bin Xiao
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for...
Defending embedded systems against buffer overflow via hardware/software (2003)
Zili Shao, Qingfeng Zhuge, Yi He
Buffer overflow attacks have been causing serious security problems for decades. With more embedded systems networked, it becomes an important research problem to defend embedded systems against...
Optimal code size reduction for software-pipelined loops on dsp applications (2002)
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try to reduce the...
Typescript (photocopy) Includes bibliographical references.